diff --git a/changelog/2022-07-26T13_16_31-05_00_reset_polarity_dsl b/changelog/2022-07-26T13_16_31-05_00_reset_polarity_dsl index 389ee8084d..4d7fe45759 100644 --- a/changelog/2022-07-26T13_16_31-05_00_reset_polarity_dsl +++ b/changelog/2022-07-26T13_16_31-05_00_reset_polarity_dsl @@ -1 +1 @@ -INTERNAL NEW: Added `unsafeToHighPolarity` and `unsafeToLowPolarity` to `Clash.Primitives.DSL`. [#2270](https://github.com/clash-lang/clash-compiler/pull/2270) +INTERNAL NEW: Added `unsafeToActiveHigh` and `unsafeToActiveLow` to `Clash.Primitives.DSL`. [#2270](https://github.com/clash-lang/clash-compiler/pull/2270) diff --git a/changelog/2023-07-13T14_49_23+02_00_rename_from_polarity b/changelog/2023-07-13T14_49_23+02_00_rename_from_polarity new file mode 100644 index 0000000000..3cd2fd3e69 --- /dev/null +++ b/changelog/2023-07-13T14_49_23+02_00_rename_from_polarity @@ -0,0 +1 @@ +DEPRECATED: `unsafeFromLowPolarity`, `unsafeFromHighPolarity`, `unsafeToLowPolarity`, `unsafeToHighPolarity` have been replaced by `unsafeFromActiveLow`, `unsafeFromActiveHigh`, `unsafeToActiveLow`, `unsafeToActiveHigh`. While former ones will continue to exist, a deprecation warning has been added pointing to the latter ones. diff --git a/clash-cores/src/Clash/Cores/Xilinx/DcFifo.hs b/clash-cores/src/Clash/Cores/Xilinx/DcFifo.hs index 631d458862..81f96977b7 100644 --- a/clash-cores/src/Clash/Cores/Xilinx/DcFifo.hs +++ b/clash-cores/src/Clash/Cores/Xilinx/DcFifo.hs @@ -177,8 +177,8 @@ dcFifo DcConfig{..} wClk wRst rClk rRst writeData rEnable = _ -> error $ show 'dcFifo <> " only supports synchronous resets" where - rstSignalR = unsafeToHighPolarity rRst - rstSignalW = unsafeToHighPolarity wRst + rstSignalR = unsafeToActiveHigh rRst + rstSignalW = unsafeToActiveHigh wRst fifoSize = natToNum @(2 ^ depth - 1) @Int dataCount = fromIntegral . Seq.length diff --git a/clash-cores/src/Clash/Cores/Xilinx/DcFifo/Internal/BlackBoxes.hs b/clash-cores/src/Clash/Cores/Xilinx/DcFifo/Internal/BlackBoxes.hs index ad17089134..ce55a2ee51 100644 --- a/clash-cores/src/Clash/Cores/Xilinx/DcFifo/Internal/BlackBoxes.hs +++ b/clash-cores/src/Clash/Cores/Xilinx/DcFifo/Internal/BlackBoxes.hs @@ -178,7 +178,7 @@ dcFifoBBTF DcConfig{..} bbCtx let domty = DSL.ety knownDomainWrite in case stripVoid domty of N.KnownDomain _ _ _ Synchronous _ _ -> - DSL.unsafeToHighPolarity "wr_rst_high" domty wRst + DSL.unsafeToActiveHigh "wr_rst_high" domty wRst N.KnownDomain _ _ _ Asynchronous _ _ -> error $ show 'dcFifoTF <> ": dcFifo only supports synchronous resets" @@ -190,7 +190,7 @@ dcFifoBBTF DcConfig{..} bbCtx let domty = DSL.ety knownDomainRead in case stripVoid domty of N.KnownDomain _ _ _ Synchronous _ _ -> - DSL.unsafeToHighPolarity "rd_rst_high" domty rRst + DSL.unsafeToActiveHigh "rd_rst_high" domty rRst N.KnownDomain _ _ _ Asynchronous _ _ -> error $ show 'dcFifoTF <> ": dcFifo only supports synchronous resets" diff --git a/clash-cores/test/Test/Cores/Xilinx/DcFifo.hs b/clash-cores/test/Test/Cores/Xilinx/DcFifo.hs index a389e03933..e8e196c54d 100644 --- a/clash-cores/test/Test/Cores/Xilinx/DcFifo.hs +++ b/clash-cores/test/Test/Cores/Xilinx/DcFifo.hs @@ -260,7 +260,7 @@ testOverflow = testCase "Overflows appropriately" $ do fifo = dcFifo @4 defConfig{dcOverflow = True} clk noRst clk noRst clk = clockGen @D3 - noRst = unsafeFromHighPolarity $ pure False + noRst = unsafeFromActiveHigh $ pure False drive15 = mealy clk noRst enableGen go 15 (pure ()) go 0 _ = (0 :: Int, Nothing) go n _ = (n-1, Just (1 :: Int)) @@ -361,11 +361,11 @@ throughFifo d _ _ feed drain wrDataList rdStalls = rdDataList where wrClk = clockGen @write - noWrRst = unsafeFromHighPolarity $ pure False + noWrRst = unsafeFromActiveHigh $ pure False wrEna = enableGen @write rdClk = clockGen @read - noRdRst = unsafeFromHighPolarity $ pure False + noRdRst = unsafeFromActiveHigh $ pure False rdEna = enableGen @read wrData = diff --git a/clash-lib/src/Clash/Primitives/DSL.hs b/clash-lib/src/Clash/Primitives/DSL.hs index 10eed5cb1c..3d7e77aa71 100644 --- a/clash-lib/src/Clash/Primitives/DSL.hs +++ b/clash-lib/src/Clash/Primitives/DSL.hs @@ -76,8 +76,8 @@ module Clash.Primitives.DSL , unsignedFromBitVector , boolFromBits - , unsafeToHighPolarity - , unsafeToLowPolarity + , unsafeToActiveHigh + , unsafeToActiveLow -- ** Operations , andExpr @@ -988,7 +988,7 @@ andExpr nm a b = do assign nm $ TExpr Bool (Identifier (Id.unsafeMake andTxt) Nothing) -- | Massage a reset to work as active-high reset. -unsafeToHighPolarity +unsafeToActiveHigh :: Backend backend => Text -- ^ Name hint @@ -997,7 +997,7 @@ unsafeToHighPolarity -> TExpr -- ^ Reset signal -> State (BlockState backend) TExpr -unsafeToHighPolarity nm dom rExpr = +unsafeToActiveHigh nm dom rExpr = case extrResetPolarity dom of ActiveHigh -> pure rExpr ActiveLow -> notExpr nm rExpr @@ -1007,7 +1007,7 @@ extrResetPolarity (Void (Just (KnownDomain _ _ _ _ _ p))) = p extrResetPolarity p = error ("Internal error: expected KnownDomain, got: " <> show p) -- | Massage a reset to work as active-low reset. -unsafeToLowPolarity +unsafeToActiveLow :: Backend backend => Text -- ^ Name hint @@ -1016,7 +1016,7 @@ unsafeToLowPolarity -> TExpr -- ^ Reset signal -> State (BlockState backend) TExpr -unsafeToLowPolarity nm dom rExpr = +unsafeToActiveLow nm dom rExpr = case extrResetPolarity dom of ActiveLow -> pure rExpr ActiveHigh -> notExpr nm rExpr diff --git a/clash-lib/src/Clash/Primitives/Xilinx/ClockGen.hs b/clash-lib/src/Clash/Primitives/Xilinx/ClockGen.hs index 68079bc96f..af300057d4 100644 --- a/clash-lib/src/Clash/Primitives/Xilinx/ClockGen.hs +++ b/clash-lib/src/Clash/Primitives/Xilinx/ClockGen.hs @@ -64,7 +64,7 @@ clockWizardDifferentialTemplate bbCtx clkWizInstName <- Id.makeBasic "clockWizardDifferential_inst" DSL.declarationReturn bbCtx "clockWizardDifferential" $ do - rstHigh <- DSL.unsafeToHighPolarity "reset" (DSL.ety knownDomIn) rst + rstHigh <- DSL.unsafeToActiveHigh "reset" (DSL.ety knownDomIn) rst pllOut <- DSL.declare "pllOut" Bit locked <- DSL.declare "locked" Bit pllLock <- DSL.boolFromBit "pllLock" locked diff --git a/clash-prelude/src/Clash/Annotations/TopEntity.hs b/clash-prelude/src/Clash/Annotations/TopEntity.hs index 9eda1dcf2b..61c769a599 100644 --- a/clash-prelude/src/Clash/Annotations/TopEntity.hs +++ b/clash-prelude/src/Clash/Annotations/TopEntity.hs @@ -84,8 +84,8 @@ topEntity clk20 rstBtn enaBtn modeBtn = -- Signal coming from the reset button is low when pressed, and high when -- not pressed. We convert this signal to the polarity of our domain with - -- /unsafeFromLowPolarity/. - rst = 'Clash.Signal.unsafeFromLowPolarity' ('Clash.Signal.unsafeFromReset' rstBtn) + -- /unsafeFromActiveLow/. + rst = 'Clash.Signal.unsafeFromActiveLow' ('Clash.Signal.unsafeFromReset' rstBtn) -- Instantiate a PLL: this stabilizes the incoming clock signal and indicates -- when the signal is stable. We're also using it to transform an incoming @@ -99,11 +99,11 @@ topEntity clk20 rstBtn enaBtn modeBtn = -- Synchronize reset to clock signal coming from PLL. We want the reset to -- remain active while the PLL is NOT stable, hence the conversion with - -- /unsafeFromLowPolarity/ + -- /unsafeFromActiveLow/ rstSync = 'Clash.Prelude.resetSynchronizer' clk50 - ('Clash.Signal.unsafeFromLowPolarity' pllStable) + ('Clash.Signal.unsafeFromActiveLow' pllStable) blinkerT :: (BitVector 8, Bool, Index 16650001) diff --git a/clash-prelude/src/Clash/Clocks/Deriving.hs b/clash-prelude/src/Clash/Clocks/Deriving.hs index 4e6006b0d8..3a9a5956db 100644 --- a/clash-prelude/src/Clash/Clocks/Deriving.hs +++ b/clash-prelude/src/Clash/Clocks/Deriving.hs @@ -51,7 +51,7 @@ derive' n = do -- Implementation of 'clocks' clkImpl <- [| Clock SSymbol Nothing |] lockImpl <- [| unsafeSynchronizer clockGen clockGen - (unsafeToLowPolarity $(varE rst)) |] + (unsafeToActiveLow $(varE rst)) |] let noInline = PragmaD $ InlineP (mkName "clocks") NoInline FunLike AllPhases clkImpls = replicate n clkImpl diff --git a/clash-prelude/src/Clash/Explicit/DDR.hs b/clash-prelude/src/Clash/Explicit/DDR.hs index e36d8f9202..27ef76b208 100644 --- a/clash-prelude/src/Clash/Explicit/DDR.hs +++ b/clash-prelude/src/Clash/Explicit/DDR.hs @@ -92,7 +92,7 @@ ddrIn# -> a -> Signal fast a -> Signal slow (a,a) -ddrIn# (Clock _ Nothing) (unsafeToHighPolarity -> hRst) (fromEnable -> ena) i0 i1 i2 = +ddrIn# (Clock _ Nothing) (unsafeToActiveHigh -> hRst) (fromEnable -> ena) i0 i1 i2 = case resetKind @fast of SAsynchronous -> goAsync diff --git a/clash-prelude/src/Clash/Explicit/Reset.hs b/clash-prelude/src/Clash/Explicit/Reset.hs index 47aceb806b..22509c2fa1 100644 --- a/clash-prelude/src/Clash/Explicit/Reset.hs +++ b/clash-prelude/src/Clash/Explicit/Reset.hs @@ -30,10 +30,16 @@ module Clash.Explicit.Reset , systemResetGen , unsafeToReset , unsafeFromReset - , unsafeToHighPolarity - , unsafeToLowPolarity + , unsafeToActiveHigh + , unsafeToActiveLow + , unsafeFromActiveHigh + , unsafeFromActiveLow + + -- * Deprecated , unsafeFromHighPolarity , unsafeFromLowPolarity + , unsafeToHighPolarity + , unsafeToLowPolarity ) where import Data.Type.Equality ((:~:)(Refl)) @@ -111,7 +117,7 @@ import GHC.TypeLits (type (+)) -- -> Signal System (BitVector 8) -- topEntity clk rst key1 = -- let (pllOut,pllStable) = altpll (SSymbol @"altpll50") clk rst --- rstSync = 'resetSynchronizer' pllOut (unsafeToHighPolarity pllStable) +-- rstSync = 'resetSynchronizer' pllOut (unsafeToActiveHigh pllStable) -- in exposeClockResetEnable leds pllOut rstSync enableGen -- where -- key1R = isRising 1 key1 @@ -184,8 +190,8 @@ resetSynchronizer clk rst = rstOut -- designed with this environment in mind. -- -- === __Example 1__ --- >>> let sampleResetN n = sampleN n . unsafeToHighPolarity --- >>> let resetFromList = unsafeFromHighPolarity . fromList +-- >>> let sampleResetN n = sampleN n . unsafeToActiveHigh +-- >>> let resetFromList = unsafeFromActiveHigh . fromList -- >>> let rst = resetFromList [True, True, False, False, True, False, False, True, True, False, True, True] -- >>> sampleResetN 12 (resetGlitchFilter d2 systemClockGen rst) -- [True,True,True,True,False,False,False,False,False,True,True,True] @@ -230,7 +236,7 @@ resetGlitchFilter SNat clk rst = -- -- Example: -- --- >>> let sampleWithReset = sampleN 8 . unsafeToHighPolarity +-- >>> let sampleWithReset = sampleN 8 . unsafeToActiveHigh -- >>> sampleWithReset (holdReset @System clockGen enableGen (SNat @2) (resetGenN (SNat @3))) -- [True,True,True,True,True,False,False,False] -- @@ -239,7 +245,7 @@ resetGlitchFilter SNat clk rst = -- intermediate assertions of the reset signal: -- -- >>> let rst = fromList [True, False, False, False, True, False, False, False] --- >>> sampleWithReset (holdReset @System clockGen enableGen (SNat @2) (unsafeFromHighPolarity rst)) +-- >>> sampleWithReset (holdReset @System clockGen enableGen (SNat @2) (unsafeFromActiveHigh rst)) -- [True,True,True,False,True,True,True,False] -- holdReset @@ -255,7 +261,7 @@ holdReset -- ^ Reset to extend -> Reset dom holdReset clk en SNat rst = - unsafeFromHighPolarity ((/=maxBound) <$> counter) + unsafeFromActiveHigh ((/=maxBound) <$> counter) where counter :: Signal dom (Index (n+1)) counter = register clk rst en 0 (satSucc SatBound <$> counter) diff --git a/clash-prelude/src/Clash/Explicit/Signal.hs b/clash-prelude/src/Clash/Explicit/Signal.hs index 1e3d28bbb0..3eb05f71d9 100644 --- a/clash-prelude/src/Clash/Explicit/Signal.hs +++ b/clash-prelude/src/Clash/Explicit/Signal.hs @@ -206,10 +206,10 @@ module Clash.Explicit.Signal , Reset , unsafeToReset , unsafeFromReset - , unsafeToHighPolarity - , unsafeToLowPolarity - , unsafeFromHighPolarity - , unsafeFromLowPolarity + , unsafeToActiveHigh + , unsafeToActiveLow + , unsafeFromActiveHigh + , unsafeFromActiveLow -- * Basic circuit functions , andEnable , enable -- DEPRECATED @@ -267,6 +267,12 @@ module Clash.Explicit.Signal , readFromBiSignal , writeToBiSignal , mergeBiSignalOuts + + -- * Deprecated + , unsafeFromHighPolarity + , unsafeFromLowPolarity + , unsafeToHighPolarity + , unsafeToLowPolarity ) where @@ -813,7 +819,7 @@ simulateB_lazy f = simulate_lazy (bundle . f . unbundle) -- | Like 'fromList', but resets on reset and has a defined reset value. -- --- >>> let rst = unsafeFromHighPolarity (fromList [True, True, False, False, True, False]) +-- >>> let rst = unsafeFromActiveHigh (fromList [True, True, False, False, True, False]) -- >>> let res = fromListWithReset @System rst Nothing [Just 'a', Just 'b', Just 'c'] -- >>> sampleN 6 res -- [Nothing,Nothing,Just 'a',Just 'b',Nothing,Just 'a'] @@ -827,7 +833,7 @@ fromListWithReset -> [a] -> Signal dom a fromListWithReset rst resetValue vals = - go (unsafeToHighPolarity rst) vals + go (unsafeToActiveHigh rst) vals where go (r :- rs) _ | r = resetValue :- go rs vals go (_ :- rs) [] = deepErrorX "fromListWithReset: input ran out" :- go rs [] diff --git a/clash-prelude/src/Clash/Intel/ClockGen.hs b/clash-prelude/src/Clash/Intel/ClockGen.hs index 8d67edc831..08f6d7d63a 100644 --- a/clash-prelude/src/Clash/Intel/ClockGen.hs +++ b/clash-prelude/src/Clash/Intel/ClockGen.hs @@ -77,13 +77,13 @@ import Clash.Signal.Internal -- where -- (clk, pllStable) = -- 'altpll' \@'Clash.Signal.System' ('SSymbol' \@\"altpll50to100\") clkInp --- ('Clash.Signal.unsafeFromLowPolarity' rstInp) --- rst = 'Clash.Signal.resetSynchronizer' clk ('Clash.Signal.unsafeFromLowPolarity' pllStable) +-- ('Clash.Signal.unsafeFromActiveLow' rstInp) +-- rst = 'Clash.Signal.resetSynchronizer' clk ('Clash.Signal.unsafeFromActiveLow' pllStable) -- @ -- -- 'Clash.Signal.resetSynchronizer' will keep the reset asserted when -- @pllStable@ is 'False', hence the use of --- @'Clash.Signal.unsafeFromLowPolarity' pllStable@. Your circuit will have +-- @'Clash.Signal.unsafeFromActiveLow' pllStable@. Your circuit will have -- signals of type @'Signal' 'Clash.Signal.System'@ and all the clocks and -- resets of your components will be the @clk@ and @rst@ signals generated here -- (modulo local resets, which will be based on @rst@ or never asserted at all @@ -179,13 +179,13 @@ altpll !_ = knownDomain @domIn `seq` knownDomain @domOut `seq` clocks -- where -- (clk :: 'Clock' 'Clash.Signal.System', pllStable :: 'Signal' 'Clash.Signal.System' 'Bool') -- 'alteraPll' ('SSymbol' \@\"alterapll50to100\") clkInp --- ('Clash.Signal.unsafeFromLowPolarity' rstInp) --- rst = 'Clash.Signal.resetSynchronizer' clk ('Clash.Signal.unsafeFromLowPolarity' pllStable) +-- ('Clash.Signal.unsafeFromActiveLow' rstInp) +-- rst = 'Clash.Signal.resetSynchronizer' clk ('Clash.Signal.unsafeFromActiveLow' pllStable) -- @ -- -- 'Clash.Signal.resetSynchronizer' will keep the reset asserted when -- @pllStable@ is 'False', hence the use of --- @'Clash.Signal.unsafeFromLowPolarity' pllStable@. Your circuit will have +-- @'Clash.Signal.unsafeFromActiveLow' pllStable@. Your circuit will have -- signals of type @'Signal' 'Clash.Signal.System'@ and all the clocks and -- resets of your components will be the @clk@ and @rst@ signals generated here -- (modulo local resets, which will be based on @rst@ or never asserted at all diff --git a/clash-prelude/src/Clash/Signal.hs b/clash-prelude/src/Clash/Signal.hs index fefbcabf51..784336e14c 100644 --- a/clash-prelude/src/Clash/Signal.hs +++ b/clash-prelude/src/Clash/Signal.hs @@ -136,10 +136,10 @@ module Clash.Signal , Reset , unsafeToReset , unsafeFromReset - , unsafeToHighPolarity - , unsafeToLowPolarity - , unsafeFromHighPolarity - , unsafeFromLowPolarity + , unsafeToActiveHigh + , unsafeToActiveLow + , unsafeFromActiveHigh + , unsafeFromActiveLow #ifdef CLASH_MULTIPLE_HIDDEN , convertReset #endif @@ -262,6 +262,12 @@ module Clash.Signal , HiddenClockName , HiddenResetName , HiddenEnableName + + -- * Deprecated + , unsafeFromHighPolarity + , unsafeFromLowPolarity + , unsafeToHighPolarity + , unsafeToLowPolarity ) where @@ -417,7 +423,7 @@ topEntity -> Signal System (BitVector 8) topEntity clk rst key1 = let (pllOut,pllStable) = 'Clash.Intel.ClockGen.altpll' (SSymbol \@\"altpll50\") clk rst - rstSync = 'resetSynchronizer' pllOut (unsafeToHighPolarity pllStable) + rstSync = 'resetSynchronizer' pllOut (unsafeToActiveHigh pllStable) in 'exposeClockResetEnable' leds pllOut rstSync enableGen where key1R = isRising 1 key1 @@ -434,7 +440,7 @@ topEntity -> Signal System (BitVector 8) topEntity clk rst key1 = let (pllOut,pllStable) = 'Clash.Intel.ClockGen.altpll' (SSymbol \@\"altpll50\") clk rst - rstSync = 'resetSynchronizer' pllOut (unsafeToHighPolarity pllStable) + rstSync = 'resetSynchronizer' pllOut (unsafeToActiveHigh pllStable) in 'withClockResetEnable' pllOut rstSync enableGen leds where key1R = isRising 1 key1 @@ -2234,7 +2240,7 @@ unsafeSynchronizer = -- -- Example: -- --- >>> sampleN @System 8 (unsafeToHighPolarity (holdReset (SNat @2))) +-- >>> sampleN @System 8 (unsafeToActiveHigh (holdReset (SNat @2))) -- [True,True,True,False,False,False,False,False] -- -- 'holdReset' holds the reset for an additional 2 clock cycles for a total @@ -2252,7 +2258,7 @@ holdReset m = -- | Like 'fromList', but resets on reset and has a defined reset value. -- --- >>> let rst = unsafeFromHighPolarity (fromList [True, True, False, False, True, False]) +-- >>> let rst = unsafeFromActiveHigh (fromList [True, True, False, False, True, False]) -- >>> let res = withReset rst (fromListWithReset Nothing [Just 'a', Just 'b', Just 'c']) -- >>> sampleN @System 6 res -- [Nothing,Nothing,Just 'a',Just 'b',Nothing,Just 'a'] diff --git a/clash-prelude/src/Clash/Signal/Internal.hs b/clash-prelude/src/Clash/Signal/Internal.hs index e246eb02c5..cdbc0b390f 100644 --- a/clash-prelude/src/Clash/Signal/Internal.hs +++ b/clash-prelude/src/Clash/Signal/Internal.hs @@ -95,10 +95,10 @@ module Clash.Signal.Internal , Reset(..) , unsafeToReset , unsafeFromReset - , unsafeToHighPolarity - , unsafeToLowPolarity - , unsafeFromHighPolarity - , unsafeFromLowPolarity + , unsafeToActiveHigh + , unsafeToActiveLow + , unsafeFromActiveHigh + , unsafeFromActiveLow , invertReset -- * Basic circuits , delay# @@ -153,6 +153,12 @@ module Clash.Signal.Internal , traverse# -- * EXTREMELY EXPERIMENTAL , joinSignal# + + -- * Deprecated + , unsafeFromHighPolarity + , unsafeFromLowPolarity + , unsafeToHighPolarity + , unsafeToLowPolarity ) where @@ -1084,7 +1090,7 @@ resetGen = resetGenN (SNat @1) -- -- Example usage: -- --- >>> sampleN 7 (unsafeToHighPolarity (resetGenN @System d3)) +-- >>> sampleN 7 (unsafeToActiveHigh (resetGenN @System d3)) -- [True,True,True,False,False,False,False] -- -- __NB__: While this can be used in the @testBench@ function, it cannot be @@ -1097,7 +1103,7 @@ resetGenN -> Reset dom resetGenN n = let asserted = replicate (snatToNum n) True in - unsafeFromHighPolarity (fromList (asserted ++ repeat False)) + unsafeFromActiveHigh (fromList (asserted ++ repeat False)) {-# ANN resetGenN hasBlackBox #-} -- See: https://github.com/clash-lang/clash-compiler/pull/2511 {-# CLASH_OPAQUE resetGenN #-} @@ -1128,15 +1134,33 @@ resetPolarityProxy _proxy = -- loops. In case of synchronous resets it can lead to -- in the presence of -- asynchronous resets. -unsafeToHighPolarity +unsafeToActiveHigh :: forall dom . KnownDomain dom => Reset dom -> Signal dom Bool -unsafeToHighPolarity (unsafeFromReset -> r) = +unsafeToActiveHigh (unsafeFromReset -> r) = case resetPolarityProxy (Proxy @dom) of SActiveHigh -> r SActiveLow -> not <$> r +{-# INLINE unsafeToActiveHigh #-} + +-- | Convert a reset to an active high reset. Has no effect if reset is already +-- an active high reset. Is unsafe because it can introduce: +-- +-- * +-- +-- For asynchronous resets it is unsafe because it can cause combinatorial +-- loops. In case of synchronous resets it can lead to +-- in the presence of +-- asynchronous resets. +unsafeToHighPolarity + :: forall dom + . KnownDomain dom + => Reset dom + -> Signal dom Bool +unsafeToHighPolarity = unsafeToActiveHigh +{-# DEPRECATED unsafeToHighPolarity "Use 'unsafeToActiveHigh' instead. This function will be removed in Clash 1.12." #-} {-# INLINE unsafeToHighPolarity #-} -- | Convert a reset to an active low reset. Has no effect if reset is already @@ -1148,15 +1172,33 @@ unsafeToHighPolarity (unsafeFromReset -> r) = -- loops. In case of synchronous resets it can lead to -- in the presence of -- asynchronous resets. -unsafeToLowPolarity +unsafeToActiveLow :: forall dom . KnownDomain dom => Reset dom -> Signal dom Bool -unsafeToLowPolarity (unsafeFromReset -> r) = +unsafeToActiveLow (unsafeFromReset -> r) = case resetPolarityProxy (Proxy @dom) of SActiveHigh -> not <$> r SActiveLow -> r +{-# INLINE unsafeToActiveLow #-} + +-- | Convert a reset to an active low reset. Has no effect if reset is already +-- an active low reset. It is unsafe because it can introduce: +-- +-- * +-- +-- For asynchronous resets it is unsafe because it can cause combinatorial +-- loops. In case of synchronous resets it can lead to +-- in the presence of +-- asynchronous resets. +unsafeToLowPolarity + :: forall dom + . KnownDomain dom + => Reset dom + -> Signal dom Bool +unsafeToLowPolarity = unsafeToActiveLow +{-# DEPRECATED unsafeToLowPolarity "Use 'unsafeToActiveLow' instead. This function will be removed in Clash 1.12." #-} {-# INLINE unsafeToLowPolarity #-} -- | 'unsafeFromReset' is unsafe because it can introduce: @@ -1168,8 +1210,8 @@ unsafeToLowPolarity (unsafeFromReset -> r) = -- in the presence of -- asynchronous resets. -- --- __NB__: You probably want to use 'unsafeToLowPolarity' or --- 'unsafeToHighPolarity'. +-- __NB__: You probably want to use 'unsafeToActiveLow' or +-- 'unsafeToActiveHigh'. unsafeFromReset :: Reset dom -> Signal dom Bool @@ -1183,8 +1225,8 @@ unsafeFromReset (Reset r) = r -- it can lead to -- issues in the presence of asynchronous resets. -- --- __NB__: You probably want to use 'unsafeFromLowPolarity' or --- 'unsafeFromHighPolarity'. +-- __NB__: You probably want to use 'unsafeFromActiveLow' or +-- 'unsafeFromActiveHigh'. unsafeToReset :: Signal dom Bool -> Reset dom @@ -1206,7 +1248,24 @@ unsafeFromHighPolarity => Signal dom Bool -- ^ Reset signal that's 'True' when active, and 'False' when inactive. -> Reset dom -unsafeFromHighPolarity r = +unsafeFromHighPolarity = unsafeFromActiveHigh +{-# DEPRECATED unsafeFromHighPolarity "Use 'unsafeFromActiveHigh' instead. This function will be removed in Clash 1.12." #-} +{-# INLINE unsafeFromHighPolarity #-} + +-- | Interpret a signal of bools as an active high reset and convert it to +-- a reset signal corresponding to the domain's setting. +-- +-- For asynchronous resets it is unsafe because it can cause combinatorial +-- loops. In case of synchronous resets it can lead to +-- in the presence of +-- asynchronous resets. +unsafeFromActiveHigh + :: forall dom + . KnownDomain dom + => Signal dom Bool + -- ^ Reset signal that's 'True' when active, and 'False' when inactive. + -> Reset dom +unsafeFromActiveHigh r = unsafeToReset $ case resetPolarityProxy (Proxy @dom) of SActiveHigh -> r @@ -1225,7 +1284,24 @@ unsafeFromLowPolarity => Signal dom Bool -- ^ Reset signal that's 'False' when active, and 'True' when inactive. -> Reset dom -unsafeFromLowPolarity r = +unsafeFromLowPolarity = unsafeFromActiveLow +{-# DEPRECATED unsafeFromLowPolarity "Use 'unsafeFromActiveLow' instead. This function will be removed in Clash 1.12." #-} +{-# INLINE unsafeFromLowPolarity #-} + +-- | Interpret a signal of bools as an active low reset and convert it to +-- a reset signal corresponding to the domain's setting. +-- +-- For asynchronous resets it is unsafe because it can cause combinatorial +-- loops. In case of synchronous resets it can lead to +-- in the presence of +-- asynchronous resets. +unsafeFromActiveLow + :: forall dom + . KnownDomain dom + => Signal dom Bool + -- ^ Reset signal that's 'False' when active, and 'True' when inactive. + -> Reset dom +unsafeFromActiveLow r = unsafeToReset $ case resetPolarityProxy (Proxy @dom) of SActiveHigh -> not <$> r @@ -1371,7 +1447,7 @@ asyncRegister# -- ^ Reset value -> Signal dom a -> Signal dom a -asyncRegister# clk (unsafeToHighPolarity -> rst) (fromEnable -> ena) initVal resetVal = +asyncRegister# clk (unsafeToActiveHigh -> rst) (fromEnable -> ena) initVal resetVal = go (registerPowerup# clk initVal) rst ena where go o (r :- rs) enas@(~(e :- es)) as@(~(x :- xs)) = @@ -1401,7 +1477,7 @@ syncRegister# -- ^ Reset value -> Signal dom a -> Signal dom a -syncRegister# clk (unsafeToHighPolarity -> rst) (fromEnable -> ena) initVal resetVal = +syncRegister# clk (unsafeToActiveHigh -> rst) (fromEnable -> ena) initVal resetVal = go (registerPowerup# clk initVal) rst ena where go o rt@(~(r :- rs)) enas@(~(e :- es)) as@(~(x :- xs)) = diff --git a/clash-prelude/src/Clash/Tutorial.hs b/clash-prelude/src/Clash/Tutorial.hs index 74ba87fca2..54c67d388f 100644 --- a/clash-prelude/src/Clash/Tutorial.hs +++ b/clash-prelude/src/Clash/Tutorial.hs @@ -924,8 +924,8 @@ topEntity topEntity clk rst = 'exposeClockResetEnable' ('mealy' blinkerT (1,False,0) . Clash.Prelude.isRising 1) pllOut rstSync 'enableGen' where - (pllOut,pllStable) = 'Clash.Intel.ClockGen.altpll' \@Dom100 (SSymbol \@\"altpll100\") clk ('Clash.Signal.unsafeFromLowPolarity' rst) - rstSync = 'Clash.Signal.resetSynchronizer' pllOut ('Clash.Signal.unsafeFromLowPolarity' pllStable) + (pllOut,pllStable) = 'Clash.Intel.ClockGen.altpll' \@Dom100 (SSymbol \@\"altpll100\") clk ('Clash.Signal.unsafeFromActiveLow' rst) + rstSync = 'Clash.Signal.resetSynchronizer' pllOut ('Clash.Signal.unsafeFromActiveLow' pllStable) blinkerT (leds,mode,cntr) key1R = ((leds',mode',cntr'),leds) where @@ -2505,8 +2505,8 @@ topEntity topEntity clk rst = 'exposeClockResetEnable' ('mealy' blinkerT (1,False,0) . Clash.Prelude.isRising 1) pllOut rstSync 'enableGen' where - (pllOut,pllStable) = 'Clash.Intel.ClockGen.altpll' \@Dom100 (SSymbol \@\"altpll100\") clk ('Clash.Signal.unsafeFromLowPolarity' rst) - rstSync = 'Clash.Signal.resetSynchronizer' pllOut ('Clash.Signal.unsafeFromLowPolarity' pllStable) + (pllOut,pllStable) = 'Clash.Intel.ClockGen.altpll' \@Dom100 (SSymbol \@\"altpll100\") clk ('Clash.Signal.unsafeFromActiveLow' rst) + rstSync = 'Clash.Signal.resetSynchronizer' pllOut ('Clash.Signal.unsafeFromActiveLow' pllStable) blinkerT (leds,mode,cntr) key1R = ((leds',mode',cntr'),leds) where diff --git a/clash-prelude/tests/Clash/Tests/AsyncFIFOSynchronizer.hs b/clash-prelude/tests/Clash/Tests/AsyncFIFOSynchronizer.hs index 5d5d74d0ca..19220d3877 100644 --- a/clash-prelude/tests/Clash/Tests/AsyncFIFOSynchronizer.hs +++ b/clash-prelude/tests/Clash/Tests/AsyncFIFOSynchronizer.hs @@ -1053,8 +1053,8 @@ fifoOperations racts wacts = (bundle (rAllDone, rel), bundle (wAllDone, wel)) wclk = clockGen @wdom -- Not resetting makes the test easier to interpret and actual proper testing -- of reset behaviour is a lot more involved. - noRRst = unsafeFromHighPolarity @rdom (pure False) - noWRst = unsafeFromHighPolarity @wdom (pure False) + noRRst = unsafeFromActiveHigh @rdom (pure False) + noWRst = unsafeFromActiveHigh @wdom (pure False) (wdone, wact) = unbundle $ fromList $ P.zip (P.repeat False) wacts <> P.repeat (True, WNoOp) (rdone, ract) = diff --git a/clash-prelude/tests/Clash/Tests/Reset.hs b/clash-prelude/tests/Clash/Tests/Reset.hs index c526e85a92..3a3113de97 100644 --- a/clash-prelude/tests/Clash/Tests/Reset.hs +++ b/clash-prelude/tests/Clash/Tests/Reset.hs @@ -20,10 +20,10 @@ createDomain vSystem{vName="Low", vResetPolarity=ActiveLow} createDomain vSystem{vName="NoInit", vInitBehavior=Unknown} sampleResetN :: KnownDomain dom => Int -> Reset dom -> [Bool] -sampleResetN n = sampleN n . unsafeToHighPolarity +sampleResetN n = sampleN n . unsafeToActiveHigh resetFromList :: KnownDomain dom => [Bool] -> Reset dom -resetFromList = unsafeFromHighPolarity . fromList +resetFromList = unsafeFromActiveHigh . fromList onePeriodGlitchReset :: KnownDomain dom => Reset dom onePeriodGlitchReset = diff --git a/clash-prelude/tests/Clash/Tests/Signal.hs b/clash-prelude/tests/Clash/Tests/Signal.hs index b2b6a7c420..2c4f119cbd 100644 --- a/clash-prelude/tests/Clash/Tests/Signal.hs +++ b/clash-prelude/tests/Clash/Tests/Signal.hs @@ -113,7 +113,7 @@ tests = "Implicit" [ -- See: https://github.com/clash-lang/clash-compiler/pull/655 let rst0 = fromList [True, True, False, False, True, True] - rst1 = unsafeFromHighPolarity rst0 + rst1 = unsafeFromActiveHigh rst0 reg = register 'a' (pure 'b') #ifdef CLASH_MULTIPLE_HIDDEN sig = withReset rst1 reg diff --git a/examples/Blinker.hs b/examples/Blinker.hs index 3e2c58bea8..a93e1bb7ef 100644 --- a/examples/Blinker.hs +++ b/examples/Blinker.hs @@ -65,8 +65,8 @@ topEntity clk20 rstBtn modeBtn = -- Signal coming from the reset button is low when pressed, and high when -- not pressed. We convert this signal to the polarity of our domain with - -- 'unsafeFromLowPolarity'. - rst = unsafeFromLowPolarity rstBtn + -- 'unsafeFromActiveLow'. + rst = unsafeFromActiveLow rstBtn -- Instantiate a PLL: this stabilizes the incoming clock signal and indicates -- when the signal is stable. We're also using it to transform an incoming @@ -80,11 +80,11 @@ topEntity clk20 rstBtn modeBtn = -- Synchronize reset to clock signal coming from PLL. We want the reset to -- remain active while the PLL is NOT stable, hence the conversion with - -- 'unsafeFromLowPolarity' + -- 'unsafeFromActiveLow' rstSync = resetSynchronizer clk50 - (unsafeFromLowPolarity pllStable) + (unsafeFromActiveLow pllStable) flipMode :: LedMode -> LedMode flipMode Rotate = Complement diff --git a/tests/shouldwork/CoSim/Register.hs b/tests/shouldwork/CoSim/Register.hs index 0645d8ee87..a87eddbf89 100644 --- a/tests/shouldwork/CoSim/Register.hs +++ b/tests/shouldwork/CoSim/Register.hs @@ -12,7 +12,7 @@ verilog_register -> Reset d -> Signal d (Signed 64) -> Signal d (Signed 64) -verilog_register clk (unsafeToHighPolarity -> arst) x = [verilog| +verilog_register clk (unsafeToActiveHigh -> arst) x = [verilog| parameter data_width = 64; input #{clk}; diff --git a/tests/shouldwork/Cores/Xilinx/DcFifo/Basic.hs b/tests/shouldwork/Cores/Xilinx/DcFifo/Basic.hs index b500dece35..2914b47791 100644 --- a/tests/shouldwork/Cores/Xilinx/DcFifo/Basic.hs +++ b/tests/shouldwork/Cores/Xilinx/DcFifo/Basic.hs @@ -81,7 +81,7 @@ testBench = done (pack <$> fifoData maxOut) (fExpectedData <$> fsmOut) (fDone <$> fsmOut) clk = tbClockGen (not <$> done) - noRst = unsafeFromHighPolarity $ pure False + noRst = unsafeFromActiveHigh $ pure False en = enableGen -- See: https://github.com/clash-lang/clash-compiler/pull/2511 {-# CLASH_OPAQUE testBench #-} diff --git a/tests/shouldwork/Cores/Xilinx/DcFifo/Lfsr.hs b/tests/shouldwork/Cores/Xilinx/DcFifo/Lfsr.hs index cdd3e2267a..12ea82f647 100644 --- a/tests/shouldwork/Cores/Xilinx/DcFifo/Lfsr.hs +++ b/tests/shouldwork/Cores/Xilinx/DcFifo/Lfsr.hs @@ -120,8 +120,8 @@ mkTestBench cFifo = done where (rClk, wClk) = biTbClockGen (not <$> done) - noRRst = unsafeFromHighPolarity $ pure False - noWRst = unsafeFromHighPolarity $ pure False + noRRst = unsafeFromActiveHigh $ pure False + noWRst = unsafeFromActiveHigh $ pure False rEna = enableGen wEna = enableGen diff --git a/tests/shouldwork/Cores/Xilinx/TdpBlockRam.hs b/tests/shouldwork/Cores/Xilinx/TdpBlockRam.hs index 055998f8d5..f38a668cdf 100644 --- a/tests/shouldwork/Cores/Xilinx/TdpBlockRam.hs +++ b/tests/shouldwork/Cores/Xilinx/TdpBlockRam.hs @@ -31,10 +31,10 @@ topEntity {-# CLASH_OPAQUE topEntity #-} noRstA :: Reset A -noRstA = unsafeFromHighPolarity (pure False) +noRstA = unsafeFromActiveHigh (pure False) noRstB :: Reset B -noRstB = unsafeFromHighPolarity (pure False) +noRstB = unsafeFromActiveHigh (pure False) tb :: ( KnownNat n0, KnownNat n1, KnownNat n2, KnownNat n3 diff --git a/tests/shouldwork/Cores/Xilinx/XpmCdcArraySingleTypes.hs b/tests/shouldwork/Cores/Xilinx/XpmCdcArraySingleTypes.hs index 9eea5893f7..2ab8f32f74 100644 --- a/tests/shouldwork/Cores/Xilinx/XpmCdcArraySingleTypes.hs +++ b/tests/shouldwork/Cores/Xilinx/XpmCdcArraySingleTypes.hs @@ -14,7 +14,7 @@ createDomain vXilinxSystem{vName="D10", vPeriod=hzToPeriod 100e6} createDomain vXilinxSystem{vName="D11", vPeriod=hzToPeriod 110e6} noRst :: KnownDomain dom => Reset dom -noRst = unsafeFromHighPolarity (pure False) +noRst = unsafeFromActiveHigh (pure False) tb :: forall a b stages width n . diff --git a/tests/shouldwork/Cores/Xilinx/XpmCdcGrayTypes.hs b/tests/shouldwork/Cores/Xilinx/XpmCdcGrayTypes.hs index fb2a949283..a5827bf82d 100644 --- a/tests/shouldwork/Cores/Xilinx/XpmCdcGrayTypes.hs +++ b/tests/shouldwork/Cores/Xilinx/XpmCdcGrayTypes.hs @@ -14,7 +14,7 @@ createDomain vXilinxSystem{vName="D10", vPeriod=hzToPeriod 100e6} createDomain vXilinxSystem{vName="D11", vPeriod=hzToPeriod 110e6} noRst :: KnownDomain dom => Reset dom -noRst = unsafeFromHighPolarity (pure False) +noRst = unsafeFromActiveHigh (pure False) tb :: forall a b width stages n . diff --git a/tests/shouldwork/Cores/Xilinx/XpmCdcHandshakeTypes.hs b/tests/shouldwork/Cores/Xilinx/XpmCdcHandshakeTypes.hs index c0eb101e27..c6f75eea69 100644 --- a/tests/shouldwork/Cores/Xilinx/XpmCdcHandshakeTypes.hs +++ b/tests/shouldwork/Cores/Xilinx/XpmCdcHandshakeTypes.hs @@ -18,7 +18,7 @@ createDomain vXilinxSystem{vName="D11", vPeriod=hzToPeriod 110e6} data State = WaitForDeassert | WaitForAssert deriving (Generic, NFDataX) noRst :: KnownDomain dom => Reset dom -noRst = unsafeFromHighPolarity (pure False) +noRst = unsafeFromActiveHigh (pure False) -- | Transfer 1, 2, 3, ... to destination domain srcFsm :: diff --git a/tests/shouldwork/Cores/Xilinx/XpmCdcSingleTypes.hs b/tests/shouldwork/Cores/Xilinx/XpmCdcSingleTypes.hs index c3068b1515..c84471386c 100644 --- a/tests/shouldwork/Cores/Xilinx/XpmCdcSingleTypes.hs +++ b/tests/shouldwork/Cores/Xilinx/XpmCdcSingleTypes.hs @@ -16,7 +16,7 @@ createDomain vXilinxSystem{vName="D10", vPeriod=hzToPeriod 100e6} createDomain vXilinxSystem{vName="D11", vPeriod=hzToPeriod 110e6} noRst :: KnownDomain dom => Reset dom -noRst = unsafeFromHighPolarity (pure False) +noRst = unsafeFromActiveHigh (pure False) tb :: forall a b stages n . diff --git a/tests/shouldwork/Issues/T1742.hs b/tests/shouldwork/Issues/T1742.hs index d69358e7aa..45fcf0438c 100644 --- a/tests/shouldwork/Issues/T1742.hs +++ b/tests/shouldwork/Issues/T1742.hs @@ -21,7 +21,7 @@ topEntity -> "LED" ::: Signal Bank2C (BitVector 4) topEntity clk rstnButton = exposeClockResetEnable top clk rst en where en = enableGen - rst = unsafeFromLowPolarity rstnButton + rst = unsafeFromActiveLow rstnButton rstSync = resetSynchronizer clk rst makeTopEntityWithName 'topEntity "shell" diff --git a/tests/shouldwork/Netlist/T1766.hs b/tests/shouldwork/Netlist/T1766.hs index 2eee6e8e8a..812101f3f3 100644 --- a/tests/shouldwork/Netlist/T1766.hs +++ b/tests/shouldwork/Netlist/T1766.hs @@ -44,7 +44,7 @@ knightrider clk rst ena = pack <$> leds topEntity :: Clock System -> Signal System Bool -> Signal System (BitVector 8) topEntity clk rstBool = knightrider clk rst enableGen where - rst = unsafeFromLowPolarity rstBool + rst = unsafeFromActiveLow rstBool testPath :: FilePath testPath = "tests/shouldwork/Netlist/T1766.hs" diff --git a/tests/shouldwork/Signal/BlockRam0.hs b/tests/shouldwork/Signal/BlockRam0.hs index 83e3037b64..7c01fd0cdf 100644 --- a/tests/shouldwork/Signal/BlockRam0.hs +++ b/tests/shouldwork/Signal/BlockRam0.hs @@ -99,6 +99,6 @@ testBench = done :> Nil) - done = expectedOutput (topEntity clk (unsafeFromHighPolarity rst0) enableGen rd wr) + done = expectedOutput (topEntity clk (unsafeFromActiveHigh rst0) enableGen rd wr) clk = tbSystemClockGen (not <$> done) rst = systemResetGen diff --git a/tests/shouldwork/Signal/BlockRam1.hs b/tests/shouldwork/Signal/BlockRam1.hs index 03ac1db6d3..3ff38a51e9 100644 --- a/tests/shouldwork/Signal/BlockRam1.hs +++ b/tests/shouldwork/Signal/BlockRam1.hs @@ -111,6 +111,6 @@ testBench = done :> Nil) - done = expectedOutput (topEntity clk (unsafeFromHighPolarity rst0) enableGen rd wr) + done = expectedOutput (topEntity clk (unsafeFromActiveHigh rst0) enableGen rd wr) clk = tbSystemClockGen (not <$> done) rst = systemResetGen diff --git a/tests/shouldwork/Signal/DelayedReset.hs b/tests/shouldwork/Signal/DelayedReset.hs index 577db0a622..dcbcc04e14 100644 --- a/tests/shouldwork/Signal/DelayedReset.hs +++ b/tests/shouldwork/Signal/DelayedReset.hs @@ -15,7 +15,7 @@ topEntity clk reset en = (cycleCount, countFromReset, newResetSig) where newReset ::Reset System newReset - = unsafeFromHighPolarity newResetSig + = unsafeFromActiveHigh newResetSig newResetSig = register clk reset en True diff --git a/tests/shouldwork/Signal/DualBlockRamDefinitions.hs b/tests/shouldwork/Signal/DualBlockRamDefinitions.hs index 6727c6f62c..8bdae5bc02 100644 --- a/tests/shouldwork/Signal/DualBlockRamDefinitions.hs +++ b/tests/shouldwork/Signal/DualBlockRamDefinitions.hs @@ -117,11 +117,11 @@ clk10TH = clockGen @B clk7TH = clockGen @C noRst20 :: Reset A -noRst20 = unsafeFromHighPolarity (pure False) +noRst20 = unsafeFromActiveHigh (pure False) noRst10 :: Reset B -noRst10 = unsafeFromHighPolarity (pure False) +noRst10 = unsafeFromActiveHigh (pure False) noRst7 :: Reset C -noRst7 = unsafeFromHighPolarity (pure False) +noRst7 = unsafeFromActiveHigh (pure False) twice = concatMap (replicate d2) strictAnd !a !b = (&&) a b diff --git a/tests/shouldwork/Signal/Ram/RMulti.hs b/tests/shouldwork/Signal/Ram/RMulti.hs index 75e9c79417..864994a49a 100644 --- a/tests/shouldwork/Signal/Ram/RMulti.hs +++ b/tests/shouldwork/Signal/Ram/RMulti.hs @@ -35,8 +35,8 @@ tbOutput top wClk rClk = output Just (0, 1) :> Just (1,2) :> Nothing :> Nil rd = delay rClk enableGen 0 $ rd + 1 output = ignoreFor rClk rNoReset enableGen d2 0 $ top wClk rClk rd wrM - wNoReset = unsafeFromHighPolarity @P20 (pure False) - rNoReset = unsafeFromHighPolarity @P10 (pure False) + wNoReset = unsafeFromActiveHigh @P20 (pure False) + rNoReset = unsafeFromActiveHigh @P10 (pure False) {-# INLINE tbOutput #-} tb @@ -51,5 +51,5 @@ tb top expectedSamples = done expectedOutput = outputVerifier' rClk noReset expectedSamples done = expectedOutput output (rClk, wClk) = biTbClockGen (not <$> done) :: (Clock P10, Clock P20) - noReset = unsafeFromHighPolarity @P10 (pure False) + noReset = unsafeFromActiveHigh @P10 (pure False) {-# INLINE tb #-} diff --git a/tests/shouldwork/Signal/Ram/RWMulti.hs b/tests/shouldwork/Signal/Ram/RWMulti.hs index 4284059327..db62f8f0af 100644 --- a/tests/shouldwork/Signal/Ram/RWMulti.hs +++ b/tests/shouldwork/Signal/Ram/RWMulti.hs @@ -55,7 +55,7 @@ tbOutput top wClk rClk = output where wrD = delay wClk enableGen 0 $ wrD + 1 output = ignoreFor rClk noReset enableGen d1 0 $ top wClk rClk wrD - noReset = unsafeFromHighPolarity @rdom (pure False) + noReset = unsafeFromActiveHigh @rdom (pure False) {-# INLINE tbOutput #-} tb @@ -76,5 +76,5 @@ tb top expectedSamples = done expectedOutput = outputVerifier' rClk noReset expectedSamples done = expectedOutput output (rClk, wClk) = biTbClockGen (not <$> done) :: (Clock rdom, Clock wdom) - noReset = unsafeFromHighPolarity @rdom (pure False) + noReset = unsafeFromActiveHigh @rdom (pure False) {-# INLINE tb #-} diff --git a/tests/shouldwork/Signal/RegisterAE.hs b/tests/shouldwork/Signal/RegisterAE.hs index ca3b052b8f..6d91e1367e 100644 --- a/tests/shouldwork/Signal/RegisterAE.hs +++ b/tests/shouldwork/Signal/RegisterAE.hs @@ -52,7 +52,7 @@ topEntity clk rst en = head <$> r topEntityAE clk rst = topEntity clk arst en where - arst = unsafeFromHighPolarity (resetInput clk rst enableGen) + arst = unsafeFromActiveHigh (resetInput clk rst enableGen) en = toEnable (enableInput clk rst enableGen) -- See: https://github.com/clash-lang/clash-compiler/pull/2511 {-# CLASH_OPAQUE topEntityAE #-} diff --git a/tests/shouldwork/Signal/RegisterAR.hs b/tests/shouldwork/Signal/RegisterAR.hs index 0cbfd791d7..ecce82ba81 100644 --- a/tests/shouldwork/Signal/RegisterAR.hs +++ b/tests/shouldwork/Signal/RegisterAR.hs @@ -35,7 +35,7 @@ topEntity clk rst = head <$> r topEntityAR clk rst = topEntity clk arst where - arst = unsafeFromHighPolarity (resetInput clk rst enableGen) + arst = unsafeFromActiveHigh (resetInput clk rst enableGen) -- See: https://github.com/clash-lang/clash-compiler/pull/2511 {-# CLASH_OPAQUE topEntityAR #-} diff --git a/tests/shouldwork/Signal/RegisterSE.hs b/tests/shouldwork/Signal/RegisterSE.hs index 903e10fd7a..8d480411a2 100644 --- a/tests/shouldwork/Signal/RegisterSE.hs +++ b/tests/shouldwork/Signal/RegisterSE.hs @@ -51,7 +51,7 @@ topEntity clk rst en = head <$> r topEntitySE clk rst = topEntity clk arst en where - arst = unsafeFromHighPolarity (resetInput clk rst enableGen) + arst = unsafeFromActiveHigh (resetInput clk rst enableGen) en = toEnable (enableInput clk rst enableGen) -- See: https://github.com/clash-lang/clash-compiler/pull/2511 {-# CLASH_OPAQUE topEntitySE #-} diff --git a/tests/shouldwork/Signal/RegisterSR.hs b/tests/shouldwork/Signal/RegisterSR.hs index f534bee29e..efe32e8847 100644 --- a/tests/shouldwork/Signal/RegisterSR.hs +++ b/tests/shouldwork/Signal/RegisterSR.hs @@ -34,7 +34,7 @@ topEntity clk rst = head <$> r topEntitySR clk rst = topEntity clk srst where - srst = unsafeFromHighPolarity (resetInput clk rst enableGen) + srst = unsafeFromActiveHigh (resetInput clk rst enableGen) -- See: https://github.com/clash-lang/clash-compiler/pull/2511 {-# CLASH_OPAQUE topEntitySR #-} diff --git a/tests/shouldwork/Signal/ResetGen.hs b/tests/shouldwork/Signal/ResetGen.hs index 3050f8d185..8e47407832 100644 --- a/tests/shouldwork/Signal/ResetGen.hs +++ b/tests/shouldwork/Signal/ResetGen.hs @@ -8,7 +8,7 @@ import Clash.Explicit.Testbench topEntity :: Clock System -> Signal System (Bool, Bool) -topEntity clk = bundle (unsafeToHighPolarity r, unsafeToHighPolarity r') +topEntity clk = bundle (unsafeToActiveHigh r, unsafeToActiveHigh r') where r = resetGenN (SNat @3) r' = holdReset clk enableGen (SNat @2) r diff --git a/tests/shouldwork/Signal/ResetSynchronizer.hs b/tests/shouldwork/Signal/ResetSynchronizer.hs index d6369b6117..ea5431b216 100644 --- a/tests/shouldwork/Signal/ResetSynchronizer.hs +++ b/tests/shouldwork/Signal/ResetSynchronizer.hs @@ -21,7 +21,7 @@ testReset :: Clock circuitDom -> Reset circuitDom testReset tbClk tbRst cClk = - unsafeFromHighPolarity + unsafeFromActiveHigh $ unsafeSynchronizer tbClk cClk $ stimuliGenerator tbClk tbRst ( True diff --git a/tests/shouldwork/Xilinx/ClockWizard.hs b/tests/shouldwork/Xilinx/ClockWizard.hs index 72e057cdf2..2af28d362d 100644 --- a/tests/shouldwork/Xilinx/ClockWizard.hs +++ b/tests/shouldwork/Xilinx/ClockWizard.hs @@ -25,10 +25,10 @@ topEntity :: topEntity clkInSE clkInDiff rstIn = let f clk rst = register clk rst enableGen 0 . fmap (satSucc SatBound) (clkA, stableA) = clockWizard (SSymbol @"clk_wiz_se") clkInSE rstIn - rstA = unsafeFromLowPolarity stableA + rstA = unsafeFromActiveLow stableA (clkB, stableB) = clockWizardDifferential (SSymbol @"clk_wiz_diff") clkInDiff rstIn - rstB = unsafeFromLowPolarity stableB + rstB = unsafeFromActiveLow stableB o1 = f clkA rstA o1 o2 = f clkB rstB o2 in bundle (o1, o2)