Update RULES.md

dalance · Mar 4, 2021 · fe6681c · fe6681c
1 parent 3efc3cd
commit fe6681c
Showing 1 changed file with 27 additions and 0 deletions.
diff --git a/RULES.md b/RULES.md
@@ -75,6 +75,33 @@ end
 endmodule
 ```
 
+## default_nettype_none
+
+### Description
+
+`` `default_nettype none`` should be at the top of source code
+
+### Reason
+
+`` `default_nettype none`` can detect unintentional implicit wires
+
+### Pass example
+
+```SystemVerilog
+`default_nettype none
+module A;
+endmodule
+
+```
+
+### Fail example
+
+```SystemVerilog
+module A;
+endmodule
+
+```
+
 ## enum_with_type
 
 ### Description