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1. AXI_WB_TB AXI_WB_TB Public

   Basic UVM Testbench to verify AXI stream spec design. Added a wishbone BFM to mimic Wishbone design.

   Verilog 2

2. PULSEDETEC_OVMTB PULSEDETEC_OVMTB Public

   Simple Pulse detector RTL and OVM_TB

   SystemVerilog

3. Machine-Learning-Practice Machine-Learning-Practice Public

   This repository contains all my practice projects with Daniel and Andrei from Udemy for future reference, Complete Machine Learning & Data Science Bootcamp 2023

   Jupyter Notebook

4. UVM-TB-PRACTICE UVM-TB-PRACTICE Public

   Code Dump of Complete End to End Test Benches I practiced from references on Udemy and others.

   SystemVerilog