v1.0.2 - Fix AXI protocol violation & remove read data interleaving

Fix #19 and remove read data interleaving

The fix consists of the round-robin update:

• the core now keep last the granted master index
• the en control in slave and master switch have been updated

Both the changes make the core AXI4 compliant for address channel (more details in #19)

Read data channel with this change doesn't interleave anymore data when completion packets use different IDs.

v1.0.1 - CDC Fix Release

This release addresses a clock issue around the master interface (from the internal switches to the external master interface). A wrong clock was connected, the issue affecting the core if aclk and mstx_aclk were different.

It brings also details and corrections to the documentation.

Any users using the CDC stages of the core must upgrade to this release.

v1.0.0

• Update documentation to better explain ordering rules. States a master is not ensured to received in-order completion if use the same ID over different slaves
• Remove AXI3 backward compatibility by sizing ALOCK to a single bit. Locked accesses over the interconnect are no more supported
• Clean-up documentation
• Add IO/Parameter chapter

New Feature: Routing Table Implementation

• Issue #5: Now the core can be can be configure to forbid some master to access particular slaves
• Issue #5: A master aiming to access an unmapped memory section receives a DECERR completion
• Issue #4: Add a new assertion to ensure MSTx_ID_MASK is not configured to 0 (unsupported value)

v0.9.0

• Introduce a first decent documentation
• Fix an issue with AXI4-lite support if LAST were not tied to 1 on top interfaces

v0.8.0

First release, close to the final implementation. This version is fully usable but it doesn't implement yet timeout support and master routing. Still lack a decent documentation but the draw.io document contains figures describing the architecture.