Merge pull request #3 from embedded-office/develop

test output with STM nucleo evaluation board
embedded-office · Oct 25, 2022 · fe38e58 · fe38e58
2 parents 6957f90 + 1fafd62
commit fe38e58
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Showing 4 changed files with 15 additions and 15 deletions.
diff --git a/debug/ozone.jdebug b/debug/ozone.jdebug
@@ -23,7 +23,7 @@ void OnProjectLoad (void) {
   // Dialog-generated settings
   //
   Project.AddPathSubstitute ("../", "$(ProjectDir)");
-  Project.SetDevice ("STM32F769NI");
+  Project.SetDevice ("STM32F446ZE");
   Project.SetHostIF ("USB", "");
   Project.SetTargetIF ("SWD");
   Project.SetTIFSpeed ("4 MHz");

diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
@@ -34,7 +34,7 @@ target_sources(canopen-stm32f4xx
     config/system_stm32f4xx.c
     # driver
     driver/stm32f4xx-hal/drv_can_can1.c
-    driver/stm32f4xx-hal/drv_nvm_fmpi2c1_at24C256.c
+    driver/stm32f4xx-hal/drv_nvm_fmpi2c1_at24c256.c
     driver/stm32f4xx-hal/drv_timer_tim2.c
 )
 

diff --git a/src/config/startup_main.c b/src/config/startup_main.c
@@ -77,10 +77,10 @@ static void SystemClock_Config(void)
     RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
     RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
 
-    /* Input frequency HSE = 25MHz */
-    /* SYSCLK = ((HSE / 15) * 216) / 2 = 180 MHz */
-    RCC_OscInitStruct.PLL.PLLM = 15;
-    RCC_OscInitStruct.PLL.PLLN = 216;
+    /* Input frequency HSE = 8MHz */
+    /* SYSCLK = ((HSE / 4) * 180) / 2 = 180 MHz */
+    RCC_OscInitStruct.PLL.PLLM = 4;
+    RCC_OscInitStruct.PLL.PLLN = 180;
     RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
     RCC_OscInitStruct.PLL.PLLQ = 2;
     RCC_OscInitStruct.PLL.PLLR = 2;

diff --git a/src/driver/stm32f4xx-hal/drv_can_can1.c b/src/driver/stm32f4xx-hal/drv_can_can1.c
@@ -44,8 +44,8 @@ typedef struct PIN_ASSIGN_T {
 ******************************************************************************/
 
 /* default pin assignment: CAN_RX -> PB8, CAN_TX -> PB9 */
-#define CAN1_PIN_RX_SEL  0
-#define CAN1_PIN_TX_SEL  0
+#define CAN1_PIN_RX_SEL  1
+#define CAN1_PIN_TX_SEL  1
 
 /******************************************************************************
 * PRIVATE VARIABLES
@@ -65,14 +65,14 @@ static PIN_ASSIGN Can1Pin_Tx[] = {
 };
 
 static BAUDRATE_TBL BaudrateTbl[] = {
-    {   10000, 300, CAN_SJW_1TQ, CAN_BS1_15TQ, CAN_BS2_2TQ },  /* SP: 88,9%, ERR:     0% */
-    {   20000, 150, CAN_SJW_1TQ, CAN_BS1_15TQ, CAN_BS2_2TQ },  /* SP: 88,9%, ERR:     0% */
+    {   10000, 250, CAN_SJW_1TQ, CAN_BS1_15TQ, CAN_BS2_2TQ },  /* SP: 88,9%, ERR:     0% */
+    {   20000, 125, CAN_SJW_1TQ, CAN_BS1_15TQ, CAN_BS2_2TQ },  /* SP: 88,9%, ERR:     0% */
     {   50000,  60, CAN_SJW_1TQ, CAN_BS1_15TQ, CAN_BS2_2TQ },  /* SP: 88,9%, ERR:     0% */
-    {  125000,  24, CAN_SJW_1TQ, CAN_BS1_15TQ, CAN_BS2_2TQ },  /* SP: 88,9%, ERR:     0% */
-    {  250000,  12, CAN_SJW_1TQ, CAN_BS1_15TQ, CAN_BS2_2TQ },  /* SP: 88,9%, ERR:     0% */
-    {  500000,   6, CAN_SJW_1TQ, CAN_BS1_15TQ, CAN_BS2_2TQ },  /* SP: 88,9%, ERR:     0% */
-    {  800000,   4, CAN_SJW_1TQ, CAN_BS1_13TQ, CAN_BS2_3TQ },  /* SP: 82,4%, ERR: -0,74% */
-    { 1000000,   3, CAN_SJW_1TQ, CAN_BS1_15TQ, CAN_BS2_2TQ },  /* SP: 88,9%, ERR:     0% */
+    {  125000,  20, CAN_SJW_1TQ, CAN_BS1_15TQ, CAN_BS2_2TQ },  /* SP: 88,9%, ERR:     0% */
+    {  250000,  10, CAN_SJW_1TQ, CAN_BS1_15TQ, CAN_BS2_2TQ },  /* SP: 88,9%, ERR:     0% */
+    {  500000,   5, CAN_SJW_1TQ, CAN_BS1_15TQ, CAN_BS2_2TQ },  /* SP: 88,9%, ERR:     0% */
+    {  800000,   3, CAN_SJW_1TQ, CAN_BS1_15TQ, CAN_BS2_3TQ },  /* SP: 84,2%, ERR: -1,32% */
+    { 1000000,   3, CAN_SJW_1TQ, CAN_BS1_12TQ, CAN_BS2_2TQ },  /* SP: 86,7%, ERR:     0% */
     { 0, 0, 0, 0, 0 }
 };