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Stabilize CpuClock, make non-exhaustive, rename variants (#2899)
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* Stabilize CpuClock, make non-exhaustive, rename variants

* CHANGELOG.md

* Fix
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@bjoernQ
bjoernQ authored Jan 7, 2025
1 parent b3401bf commit 66d2eff
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Showing 14 changed files with 93 additions and 79 deletions.
1 change: 1 addition & 0 deletions esp-hal/CHANGELOG.md
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Expand Up @@ -94,6 +94,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- UART: Make `AtCmdConfig` use builder-lite pattern (#2851)
- UART: Fix naming violations for `DataBits`, `Parity`, and `StopBits` enum variants (#2893)
- UART: Remove blocking version of `read_bytes` and rename `drain_fifo` to `read_bytes` instead (#2895)
- Renamed variants of `CpuClock`, made the enum non-exhaustive (#2899)

### Fixed

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11 changes: 11 additions & 0 deletions esp-hal/MIGRATING-0.22.md
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Expand Up @@ -394,3 +394,14 @@ Full duplex does not require this, and it also creates an artificial restriction

If you were using half duplex SPI with `with_miso`,
you should now use `with_sio1` instead to get the previous behavior.

## CPU Clocks

The specific CPU clock variants are renamed from e.g. `Clock80MHz` to `_80MHz`.

```diff
- CpuClock::Clock80MHz
+ CpuClock::_80MHz
```

Additionally the enum is marked as non-exhaustive.
18 changes: 9 additions & 9 deletions esp-hal/src/clock/clocks_ll/esp32.rs
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Expand Up @@ -64,7 +64,7 @@ pub(crate) fn esp32_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClock

// Configure 320M PLL
match xtal_freq {
XtalClock::RtcXtalFreq40M => {
XtalClock::_40M => {
div_ref = 0;
div7_0 = 32;
div10_8 = 0;
Expand All @@ -73,7 +73,7 @@ pub(crate) fn esp32_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClock
bw = 3;
}

XtalClock::RtcXtalFreq26M => {
XtalClock::_26M => {
div_ref = 12;
div7_0 = 224;
div10_8 = 4;
Expand All @@ -82,7 +82,7 @@ pub(crate) fn esp32_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClock
bw = 1;
}

XtalClock::RtcXtalFreqOther(_) => {
XtalClock::Other(_) => {
div_ref = 12;
div7_0 = 224;
div10_8 = 4;
Expand All @@ -102,7 +102,7 @@ pub(crate) fn esp32_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClock

// Configure 480M PLL
match xtal_freq {
XtalClock::RtcXtalFreq40M => {
XtalClock::_40M => {
div_ref = 0;
div7_0 = 28;
div10_8 = 0;
Expand All @@ -111,7 +111,7 @@ pub(crate) fn esp32_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClock
bw = 3;
}

XtalClock::RtcXtalFreq26M => {
XtalClock::_26M => {
div_ref = 12;
div7_0 = 144;
div10_8 = 4;
Expand All @@ -120,7 +120,7 @@ pub(crate) fn esp32_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClock
bw = 1;
}

XtalClock::RtcXtalFreqOther(_) => {
XtalClock::Other(_) => {
div_ref = 12;
div7_0 = 224;
div10_8 = 4;
Expand Down Expand Up @@ -220,14 +220,14 @@ pub(crate) fn set_cpu_freq(cpu_freq_mhz: crate::clock::CpuClock) {
let per_conf;

match cpu_freq_mhz {
crate::clock::CpuClock::Clock160MHz => {
crate::clock::CpuClock::_160MHz => {
per_conf = CPU_160M;
}
crate::clock::CpuClock::Clock240MHz => {
crate::clock::CpuClock::_240MHz => {
dbias = dig_dbias_240_m;
per_conf = CPU_240M;
}
crate::clock::CpuClock::Clock80MHz => {
crate::clock::CpuClock::_80MHz => {
per_conf = CPU_80M;
}
}
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8 changes: 4 additions & 4 deletions esp-hal/src/clock/clocks_ll/esp32c2.rs
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Expand Up @@ -65,7 +65,7 @@ pub(crate) fn esp32c2_rtc_bbpll_configure(xtal_freq: XtalClock, _pll_freq: PllCl

// Configure 480M PLL
match xtal_freq {
XtalClock::RtcXtalFreq26M => {
XtalClock::_26M => {
div_ref = 12;
div7_0 = 236;
dr1 = 4;
Expand All @@ -74,7 +74,7 @@ pub(crate) fn esp32c2_rtc_bbpll_configure(xtal_freq: XtalClock, _pll_freq: PllCl
dcur = 0;
dbias = 2;
}
XtalClock::RtcXtalFreq40M | XtalClock::RtcXtalFreqOther(_) => {
XtalClock::_40M | XtalClock::Other(_) => {
div_ref = 0;
div7_0 = 8;
dr1 = 0;
Expand Down Expand Up @@ -150,8 +150,8 @@ pub(crate) fn esp32c2_rtc_freq_to_pll_mhz(cpu_clock_speed: CpuClock) {
.modify(|_, w| w.pre_div_cnt().bits(0).soc_clk_sel().bits(1));
system_control.cpu_per_conf().modify(|_, w| {
w.cpuperiod_sel().bits(match cpu_clock_speed {
CpuClock::Clock80MHz => 0,
CpuClock::Clock120MHz => 1,
CpuClock::_80MHz => 0,
CpuClock::_120MHz => 1,
})
});
}
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16 changes: 8 additions & 8 deletions esp-hal/src/clock/clocks_ll/esp32c3.rs
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Expand Up @@ -70,7 +70,7 @@ pub(crate) fn esp32c3_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClo

// Configure 480M PLL
match xtal_freq {
XtalClock::RtcXtalFreq40M => {
XtalClock::_40M => {
div_ref = 0;
div7_0 = 8;
dr1 = 0;
Expand All @@ -80,7 +80,7 @@ pub(crate) fn esp32c3_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClo
dbias = 2;
}

XtalClock::RtcXtalFreq32M => {
XtalClock::_32M => {
div_ref = 1;
div7_0 = 26;
dr1 = 1;
Expand All @@ -90,7 +90,7 @@ pub(crate) fn esp32c3_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClo
dbias = 2;
}

XtalClock::RtcXtalFreqOther(_) => {
XtalClock::Other(_) => {
div_ref = 0;
div7_0 = 8;
dr1 = 0;
Expand All @@ -110,7 +110,7 @@ pub(crate) fn esp32c3_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClo

// Configure 320M PLL
match xtal_freq {
XtalClock::RtcXtalFreq40M => {
XtalClock::_40M => {
div_ref = 0;
div7_0 = 4;
dr1 = 0;
Expand All @@ -120,7 +120,7 @@ pub(crate) fn esp32c3_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClo
dbias = 2;
}

XtalClock::RtcXtalFreq32M => {
XtalClock::_32M => {
div_ref = 1;
div7_0 = 6;
dr1 = 0;
Expand All @@ -130,7 +130,7 @@ pub(crate) fn esp32c3_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClo
dbias = 2;
}

XtalClock::RtcXtalFreqOther(_) => {
XtalClock::Other(_) => {
div_ref = 0;
div7_0 = 4;
dr1 = 0;
Expand Down Expand Up @@ -211,8 +211,8 @@ pub(crate) fn esp32c3_rtc_freq_to_pll_mhz(cpu_clock_speed: CpuClock) {
.modify(|_, w| w.pre_div_cnt().bits(0).soc_clk_sel().bits(1));
system_control.cpu_per_conf().modify(|_, w| {
w.cpuperiod_sel().bits(match cpu_clock_speed {
CpuClock::Clock80MHz => 0,
CpuClock::Clock160MHz => 1,
CpuClock::_80MHz => 0,
CpuClock::_160MHz => 1,
})
});
}
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12 changes: 6 additions & 6 deletions esp-hal/src/clock/clocks_ll/esp32s2.rs
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Expand Up @@ -23,17 +23,17 @@ pub(crate) fn set_cpu_clock(cpu_clock_speed: CpuClock) {
.set_bit()
.cpuperiod_sel()
.bits(match cpu_clock_speed {
CpuClock::Clock80MHz => 0,
CpuClock::Clock160MHz => 1,
CpuClock::Clock240MHz => 2,
CpuClock::_80MHz => 0,
CpuClock::_160MHz => 1,
CpuClock::_240MHz => 2,
})
});

rtc_cntl.reg().modify(|_, w| {
w.dig_reg_dbias_wak().bits(match cpu_clock_speed {
CpuClock::Clock80MHz => DIG_DBIAS_80M_160M,
CpuClock::Clock160MHz => DIG_DBIAS_80M_160M,
CpuClock::Clock240MHz => DIG_DBIAS_240M,
CpuClock::_80MHz => DIG_DBIAS_80M_160M,
CpuClock::_160MHz => DIG_DBIAS_80M_160M,
CpuClock::_240MHz => DIG_DBIAS_240M,
} as u8)
});

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6 changes: 3 additions & 3 deletions esp-hal/src/clock/clocks_ll/esp32s3.rs
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Expand Up @@ -17,9 +17,9 @@ pub(crate) fn set_cpu_clock(cpu_clock_speed: CpuClock) {
.set_bit()
.cpuperiod_sel()
.bits(match cpu_clock_speed {
CpuClock::Clock80MHz => 0,
CpuClock::Clock160MHz => 1,
CpuClock::Clock240MHz => 2,
CpuClock::_80MHz => 0,
CpuClock::_160MHz => 1,
CpuClock::_240MHz => 2,
})
});
}
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