From 68a22d4271cbf92c069bf2d622602ab23e2f5a77 Mon Sep 17 00:00:00 2001
From: exuanbo <exuanbo@protonmail.com>
Date: Fri, 4 Oct 2024 21:59:09 +0100
Subject: [PATCH] refactor(core): rename prop

---
 src/core/bus/bus.ts | 2 +-
 src/core/cpu/cpu.ts | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/core/bus/bus.ts b/src/core/bus/bus.ts
index 34a8bfba..9c9851e9 100644
--- a/src/core/bus/bus.ts
+++ b/src/core/bus/bus.ts
@@ -29,7 +29,7 @@ export class Bus {
   readonly address$ = new BehaviorSubject(0x00)
   readonly control$ = new BehaviorSubject(initialControlLines)
 
-  readonly controlOnClockRise$: Observable<ControlLines> = this.control$.pipe(
+  readonly clockRise$: Observable<ControlLines> = this.control$.pipe(
     filter((control, index) => (index && control.CLK)),
     share(),
   )
diff --git a/src/core/cpu/cpu.ts b/src/core/cpu/cpu.ts
index df3290a6..d93a3fc1 100644
--- a/src/core/cpu/cpu.ts
+++ b/src/core/cpu/cpu.ts
@@ -22,7 +22,7 @@ export class Cpu {
       RD:   0b1,
       MREQ: 0b1,
     })
-    yield this.bus.controlOnClockRise$.pipe(take(1))
+    yield this.bus.clockRise$.pipe(take(1))
     this.bus.setControl({
       RD:   0b0,
       MREQ: 0b0,
@@ -37,7 +37,7 @@ export class Cpu {
       WR:   0b1,
       MREQ: 0b1,
     })
-    yield this.bus.controlOnClockRise$.pipe(take(1))
+    yield this.bus.clockRise$.pipe(take(1))
     this.bus.setControl({
       WR:   0b0,
       MREQ: 0b0,