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[WIP] Add QuickLogic EOS-S3 support #1758

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[WIP] Add QuickLogic EOS-S3 support #1758

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Commits on Nov 9, 2020

  1. Updated create_ioplace.py so that IOB placement may depend on its type 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  2. Fixed a bug with QMUX fanout routes 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  3. Added a techmap for ckpad 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  4. Added dumy timings for delayless routes to satisfy VPR 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  5. Refactored routing_import.py 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  6. Changed IS0, IS1 and HSCKIN connections to QMUX to be of type CLOCK 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  7. Separate model for switchbox at QMUX locations 

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  8. Changed the VPR model for GMUX to allow using of the IC input when th… 

    …e IP input is unconnected (no CLOCK pad)

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  9. Symlinking instead of copying cells_map.v 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  10. Added import of QMUX and CAND cell timings to the rr graph 

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  11. Removed -noflatten from synth.tcl, added hint attributes to primitives. 

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  12. Added relocation of CAND cells so they occupy only even rows. 

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  13. Fixed QMUX fasm features, added CAND fasm features 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  14. Added correct SDF timing scale for route-though cells. 

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  15. Added fasm features to GMUX cells 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  16. Removed debugging prints 

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  17. Added a test for CLOCK inputs via GMUX 

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  18. Added 3rd coorintate to all Locs, GMUX tile split along the Z-axis 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  19. Added heterogeneous tiles support to the arch.xml generation scripts. 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  20. Fixed a bug with arch tilegrid dimensions. 

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  21. Fixed routing_import.py to support heterogeneous tiles. 

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  22. Changed the way in which GMUX tiles are built. 

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  23. Made CLOCK -> GMUX connections direct in the arch.xml 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  24. Partial equivalent tiles support 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  25. Added placement constraints generation for CLOCK and GMUX tiles 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  26. Fixed clock pin names definitions in data_import.py 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  27. Fixed a typo in utils/vpr_io_place.py 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  28. Added techmaps for qhsckbuff and qhsckibuff. A ckpad cell can get con… 

    …verted to a inpad cell if its parameter IO_TYPE is set to sth. other than "CLOCK"

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  29. Creating a new folder for keeping common quicklogic files 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  30. updating the testcases for clock map 

    Signed-off-by: Kishor Kumar <kkumar@quicklogic.com>
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  31. updating the testcases for clock map 

    Signed-off-by: Kishor Kumar <kkumar@quicklogic.com>
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  32. Added insertion of the GMUX_IP cell for connectionc CLOCK -> GMUX req… 

    …uired in SymbiFlow.

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  33. Updated the gclk_counter design 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  34. Added techmap for mux4x0 and mux8x0 

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  35. updating the pcf fileS 

    Signed-off-by: Kishor Kumar <kkumar@quicklogic.com>
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  36. Added a techmap that converts ckpad to a pair of CLOCK_CELL + GMUX_P 

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  37. Added (* keep *) to the ASSP cell model for VPR 

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  38. Added emission of fasm faetures enabling CLOCK cells 

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  39. Modified to rectify compilation error in Sim 

    Signed-off-by: Rakesh Moolacheri <54097448+rakeshm75@users.noreply.github.com>
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  40. Added specify block 

    Signed-off-by: Rakesh Moolacheri <54097448+rakeshm75@users.noreply.github.com>
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  41. added specify block 

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  42. Added specify block 

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  43. Added specify block 

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  44. rectified compilation error in Sim 

    Signed-off-by: Rakesh Moolacheri <54097448+rakeshm75@users.noreply.github.com>
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  45. add specify blocks into primitives to annotate SDF timings 

    Signed-off-by: Rakesh Moolacheri <54097448+rakeshm75@users.noreply.github.com>
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  46. Added specify block 

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  47. created folder for fpga interconnect 

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  48. added fpga_interconnect.sim.v file 

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  49. added sub directory fpga interconnect 

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  50. Renaming 

    Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
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  51. reverting file to support on travis 

    Signed-off-by: Kishor Kumar <kkumar@quicklogic.com>
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  52. reformat yapf compatible 

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  53. format change to support in travis 

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  54. changing the python format to support in travis 

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  55. Updating README after quicklogic folder re-organization 

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  56. removed one gclkbuff instance 

    Signed-off-by: Rakesh Moolacheri <54097448+rakeshm75@users.noreply.github.com>
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  57. Added S3 WB interface to the design 

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  58. Adding submodule with relative url quicklogic/common/utils/fasm-utils 

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  59. Fixed location handling 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  60. Added decoding of the global clock network connectivity. CAND to swit… 

    …chbox connections are now decoded properly.

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  61. Correct decoding of CLOCK and GMUX in fasm2bels 

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  62. Fixed PCF parsing in fasm2bels 

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  63. Added proper pin renaming to fasm2bels 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  64. fasm2bels code refactoring and cleanup 

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  65. Added decoding of QMUX driven by the routing network to fasm2bels 

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  66. Deleting submodule quicklogic/common/utils/quicklogic-fasm quicklogic… 

    …/common/utils/quicklogic-timings-importer to re-add with relative url

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  67. Adding submodule with relative url 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  68. Adding submodule with relative url 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  69. Path change due to restructure 

    Signed-off-by: Kishor Kumar <kkumar@mahanadi.ql-corp.com>
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  70. added another path in specify block 

    Signed-off-by: Rakesh Moolacheri <54097448+rakeshm75@users.noreply.github.com>
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  71. modified the specify block to add more paths 

    Signed-off-by: Rakesh Moolacheri <54097448+rakeshm75@users.noreply.github.com>
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  72. Added ASSP simulation model 

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  73. folder for ramfifo model 

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  74. added ramfifo simulation model 

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  75. added sub directory ramfifo 

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  76. adding the clkmap csv details 

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  77. added timescale 

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  78. adding post verilog and sdf option 

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  79. Update install.cmake 

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  80. Modified the pcf file to match PD64 pins 

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  81. Modified the pcf file to match PD64 pins 

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  82. Splitting of multi-bit ports in Quicklogic RAM models 

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  83. Added separate modes for C_FRAG and T_FRAG+B_FRAG 

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  84. Added a mode to host an entire logic_cell_macro 

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  85. Moved files 

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  86. Added ifdef GSIM for specify block 

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  87. Moving toolchain_wrappers to common and making related changes to all… 

    …ow multiple device family

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  88. Fix for generated bit file where input & output signals should not be… 

    … declared as wires

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  89. QL: install: fix fasm_to_bit install dependecies 

    Signed-off-by: Karol Gugala <kgugala@antmicro.com>
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  90. Added mapping of LUT4 directly to C_FRAG 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  91. create folder for design8 

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  92. added rtl files for design8 

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  93. create folder for design9 

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  94. added design9 files 

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  95. create folder for design10 

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  96. added test design10 files 

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  97. created folder for clock test design 

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  98. added clock test design files 

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  99. create folder for logic cell macro test 

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  100. added logic cell macro test design 

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  101. create folder for FIFO test design 

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  102. added FIFO test design files 

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  103. create folder for RAM test design 

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  104. added RAM test design files 

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  105. added sub directories for newly added test designs 

    Signed-off-by: Rakesh Moolacheri <54097448+rakeshm75@users.noreply.github.com>
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  106. modified ram model to fix port mismatch issue 

    Signed-off-by: Rakesh Moolacheri <54097448+rakeshm75@users.noreply.github.com>
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  107. Update chandalar.pcf 

    removing the C port as it is not present in rtl

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  108. correct RAM port names to match with simulation model 

    Signed-off-by: Tarachand Pagarani <tpagarani@quicklogic.com>
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  109. Fixed incorrect CAND connection handling for multi-loc cells 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  110. adding the python formatted files 

    Signed-off-by: Kishor Kumar <kkumar@qlsof01.ql-corp.com>
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  111. adding the target for selective testcases 

    Signed-off-by: Kishor Kumar <kkumar@qlsof01.ql-corp.com>
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  112. Fixed techmaps for muxes. 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  113. Added specify block 

    Signed-off-by: Rakesh Moolacheri <54097448+rakeshm75@users.noreply.github.com>
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  114. Added techmaps for splitting cells 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  115. Added the logic optimization script to the synthesis flow 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  116. Added VPR options that allow tighter packing 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  117. added specify block 

    Signed-off-by: Rakesh Moolacheri <54097448+rakeshm75@users.noreply.github.com>
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  118. reverted the changes 

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  119. added specify block 

    Signed-off-by: Rakesh Moolacheri <54097448+rakeshm75@users.noreply.github.com>
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  120. removing few testcases 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  121. Removed additional QMUX input ports from the physical db. 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  122. adding the right syntax for the specify block 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  123. adding 2 values 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  124. Update mult.sim.v 

    Signed-off-by: Kishor Kumar <61860672+kkumar23@users.noreply.github.com>
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  125. selecting tc's for all_quick_tests 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  126. ql: add cached lookahead 

    Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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  127. flow: reduce warnings output and restore travis stdout 

    Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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  128. ql: tests: remove spi_master target addition from design10 test 

    Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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  129. ql: output vpr_db directly to stdout and save to file 

    Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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  130. ql: tests: fix simulation tests with iverilog 

    Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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  131. Update mult.sim.v 

    Signed-off-by: Kishor Kumar <61860672+kkumar23@users.noreply.github.com>
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  132. Revert "ql: output vpr_db directly to stdout and save to file" 

    This reverts commit 93a6492.

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  133. ql: ram: make the ram timing sdf file not hardcoded 

    Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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  134. util: skip cell if it does not have port_directions 

    Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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  135. adding the simulation testcases 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  136. remove hidden files 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  137. ql: ram: pass the ram pb_type to use as cmake argument 

    Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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  138. ql: fix cmake dependency issue 

    Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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  139. ql: timings: fix bels definition for pp3 

    Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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  140. io_place: skip nets with no blocks 

    This can happen if considered net is e.g. not connected top level input,
or the module input is driven by a constant.

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  141. WIP: enabling local failing tests for CI check 

    Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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  142. Added annotations to GMUX cell models 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  143. Added generation of FAKE_CONST pins for tiles that can access the glo… 

    …bal const network bypassing switchboxes

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  144. Updated the LOGIC cell definition to allow using direct LUT to FF route 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  145. Updated techmap 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  146. Added pack pattern specification 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  147. bump quicklogic-timing-importer 

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  148. ql: mux8: revert to have two mux4 and a F_FRAG when mapping a mux8 

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  149. ql: pack: add packer threshold for high fanout nets on PB-LOGIC 

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  150. ql: cells_sim: re-add ASSP model to the cells sim generated file 

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  151. ql: tests: temp disable of ql tests due to unavailable device resources 

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  152. ql: install: remove un-needed scripts that are isntalled in conda 

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  153. Fixed QMUX input connections handling in fasm2bels 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  154. Added missing file. 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  155. Re-enabled previously disabled CI tests 

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  156. Initializing newly added parameter, EQN, in LUT definition 

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  157. Revert "ql: mux8: revert to have two mux4 and a F_FRAG when mapping a… 

    … mux8"

This reverts commit 13bf1c1.

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  158. Fixed invocation of pack.tcl and added it as a file to be installed. 

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  159. Adding support to allow alias name in pcf while doing fix placement. … 

    …User can either specify pin name or alias name as mentioned in pin mapping

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  160. Adding check if alias is specified or not in package section in xml 

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  161. bram init support 

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  162. add bram init test 

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  163. add bram init test 

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  164. change directory 

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  165. change directory 

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  166. Added missing EQN parameter to LUT techmaps 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  167. add INIT parameters to support simulation 

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  168. Fix the issue in IOMux pad name settings for jlink, which were set wr… 

    …ongly

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  169. Removing a print message 

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  170. Fixing an issue when pad alias is specified instead of pin name 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  171. Fixed toolchan wrapper to pass PCF and PART variables to the synth sc… 

    …ript

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  172. Fixed PCF files for cavlc_top and iir test designs 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  173. Removed the second top-level module from sha256_fullfit design 

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  174. adding testcase 

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  175. Update quicklogic_jlink.cmake 

    Adding back pinmap details

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  176. Delete RAM_16K_BLK.v 

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  177. Delete r512x16_512x16_r1024x8_1024x8.v 

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  178. Modified RAM test design 

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  179. Delete af512x16_512x16_f512x16_512x16.v 

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  180. Delete FIFO_16K_BLK.v 

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  181. Modified FIFO test design 

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  182. Delete af1024x8_1024x8_af1024x8_1024x8.v 

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  183. Delete af2048x8_2048x8.v 

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  184. Delete af512x16_512x16_f512x16_512x16.v 

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  185. Delete f512x18_512x18_f512x9_512x9.v 

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  186. Delete f2048x8_1024x16.v 

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  187. Updated FIFOs with new FIFO macros 

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  188. Delete r512x16_512x16_r1024x8_1024x8.v 

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  189. Delete r512x32_1024x16.v 

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  190. Modified RAMs with new macros 

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  191. Delete AL4S3B_FPGA_IP.v 

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  192. Delete AL4S3B_FPGA_QL_Reserved.v 

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  193. Delete AL4S3B_FPGA_Registers.v 

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  194. Delete AL4S3B_FPGA_Top.v 

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  195. Delete CMakeLists.txt 

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  196. Delete FIFO_16K_BLK.v 

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  197. Delete af512x16_512x16_f512x16_512x16.v 

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  198. Delete af512x32_512x32.v 

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  199. Delete chandalar.pcf 

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  200. Delete AL4S3B_FPGA_IP.v 

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  201. Delete AL4S3B_FPGA_QL_Reserved.v 

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  202. Delete AL4S3B_FPGA_RAMs.v 

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  203. Delete AL4S3B_FPGA_Registers.v 

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  204. Delete AL4S3B_FPGA_Top.v 

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  205. Delete CMakeLists.txt 

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  206. Delete RAM_16K_BLK.v 

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  207. Delete chandalar.pcf 

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  208. Delete r512x16_512x16_r1024x8_1024x8.v 

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  209. Delete r512x32_512x32.v 

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  210. Added more RAMs to the test case 

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  211. Fixed incorrect path to Yosys cells_sim.v file 

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  212. update fasm parameter for ram block 1 

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  213. update fasm submodule 

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  214. Fix CMake for LUT techmap test 

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  215. adding the dependency files 

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  216. adding the dependency files 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  217. Fixed a bug in pack.tcl, added splitting mux8x0 to 7xmux2x0 as a last… 

    … resort.

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  218. modified the RAM model to support initialization 

    Signed-off-by: Rakesh Moolacheri <54097448+rakeshm75@users.noreply.github.com>
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  219. Adding ramfifo files 

    Signed-off-by: Kishor Kumar <61860672+kkumar23@users.noreply.github.com>
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  220. adding compare gold file 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  221. add command file 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  222. adding designs for perf 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  223. Changed the model of CLOCK_CELL so that it is now a clock buffer for VPR 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  224. Remove not existing files from toolchain wrappers 

    Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
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  225. Update CMakeLists.txt 

    Removing wpiflash, due to licensing terms

Signed-off-by: Kishor Kumar <61860672+kkumar23@users.noreply.github.com>
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  226. Updated gclk_counter test to use SDC constraints 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  227. toolchain_wrappers: add symbiflow prefix to toolchain wrappers 

    Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
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  228. Update ql_symbiflow 

    Syntax update symbiflo_write_fasm to symbiflow_write_fasm

Signed-off-by: Kishor Kumar <61860672+kkumar23@users.noreply.github.com>
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  229. Add openocd format config generation for IOMUX 

    Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
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  230. Set output-format to jlink for jlink stage 

    Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
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  231. Add openocd to toolchain_wrappers 

    Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
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  232. jimbob: fix pads when no alias is present 

    Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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  233. Add openocd stage to cmake 

    Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
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  234. Add description of openocd stage to README 

    Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
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  235. Add openocd option to quicklogic tests 

    Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
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  236. rr_graph: remove penalty cost from switches 

    Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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  237. add designs 

    Signed-off-by: Kishor Kumar <kkumar@quicklogic.com>
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  238. add designs 

    Signed-off-by: Kishor Kumar <kkumar@quicklogic.com>
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  239. Update ql_symbiflow 

    correcting command

Signed-off-by: Kishor Kumar <61860672+kkumar23@users.noreply.github.com>
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  240. Update symbiflow_place 

    Signed-off-by: Kishor Kumar <61860672+kkumar23@users.noreply.github.com>
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  241. Update symbiflow_write_fasm2bels 

    Signed-off-by: Kishor Kumar <61860672+kkumar23@users.noreply.github.com>
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  242. Update ql_symbiflow 

    adding openocd

Signed-off-by: Kishor Kumar <61860672+kkumar23@users.noreply.github.com>
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  243. Update submodules 

    Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
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  244. Add quicklogic python packages 

    Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
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  245. Adjust quicklogic directory for make-env usage 

    Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
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  246. Add write_sdc command to fix tests building 

    Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
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  247. Add OUT_SDC to quicklogic toolchain_wrappers 

    Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
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  248. Add kokoro setup for quicklogic 

    Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
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  249. Remove unnecessary v2x dependencies 

    This changes enables the option of using custom v2x package.

Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
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  250. [FIXME] Set python version to 3.7 

    This change is required by the quicklogic-yosys conda package,
used in the quicklogic kokoro CI.

Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
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    rw1nkler committed Nov 9, 2020
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