diff --git a/codegen/z80_desc.yml b/codegen/z80_desc.yml
index a277fffd..6cc51439 100644
--- a/codegen/z80_desc.yml
+++ b/codegen/z80_desc.yml
@@ -83,13 +83,11 @@ ADD HL,$RP:
 LD (BC),A:
   cond: (x == 0) and (z == 2) and (q == 0) and (p == 0)
   mcycles:
-    # NOTE: WZH can also be 0 on Z80 clones (the VisualZ80 netlist also sets WZH to zero)
     - { type: mwrite, ab: $BC, db: $A, action: "$WZL=$C+1;$WZH=$A" }
 
 LD (DE),A:
   cond: (x == 0) and (z == 2) and (q == 0) and (p == 1)
   mcycles:
-    # NOTE: WZH can also be 0 on Z80 clones (the VisualZ80 netlist also sets WZH to zero)
     - { type: mwrite, ab: $DE, db: $A, action: "$WZL=$E+1;$WZH=$A" }
 
 LD (nn),HL:
@@ -105,7 +103,6 @@ LD (nn),A:
   mcycles:
     - { type: mread, ab: $PC++, dst: $WZL }
     - { type: mread, ab: $PC++, dst: $WZH }
-    # NOTE: WZH can also be 0 on Z80 clones (the VisualZ80 netlist also sets WZH to zero)
     - { type: mwrite, ab: $WZ++, db: $A, action: "$WZH=$A" }
 
 LD A,(BC):
@@ -432,7 +429,7 @@ LD (nn),$RP:
     - { type: mread, ab: $PC++, dst: $WZH }
     - { type: mwrite, ab: $WZ++, db: $RRPL }
     - { type: mwrite, ab: $WZ, db: $RRPH }
-  
+
 LD $RP,(nn):
   prefix: ed
   cond: (x == 1) and (z == 3) and (q == 1)
@@ -586,7 +583,7 @@ CPDR:
 INI:
   prefix: ed
   cond: (x == 2) and (y == 4) and (z == 2)
-  mcycles: 
+  mcycles:
     - { type: generic, tcycles: 1 }
     - { type: ioread, ab: $BC, dst: $DLATCH, action: "$WZ=$BC+1;$B--;" }
     - { type: mwrite, ab: "cpu->hl++", db: $DLATCH, action: "_z80_ini_ind(cpu,$DLATCH,$C+1)" }