The DSD_MNIST_Streamline project aims to design and implement a digital signal processing system utilizing the MNIST dataset. This project consists of 5 layers, with each layer structured with local_ctrl
, PU
, and temp_bram
components.
Board : Zybo z7-20
Accuracy: 100%
Total time in seconds: 0.000075 + 0.000090 + 0.000090 + 0.000089 + 0.000091 + 0.000089 + 0.000089 + 0.000090 + 0.000089 + 0.000098 = 0.000890 seconds
Milliseconds (ms): 0.000890 seconds × 1000 = 0.890 ms
Nanoseconds (ns): 0.000890 seconds × 1,000,000,000 = 890,000 ns
"The FPGA hardware accelerator is approximately 12.72 times faster."
The project is composed of the following five layers:
- Layer 1
- Layer 2
- Layer 3
- Layer 4
- Layer 5
Each layer contains the following components:
local_ctrl
: Local control modulePU
: Processing unittemp_bram
: Temporary Block RAM storage
- local_ctrl: The local control module in the first layer receives input signals and forwards them to the processing unit.
- PU: The processing unit processes the input signals and stores the results in the temporary BRAM.
- temp_bram: Memory for temporarily storing processed data.
Layers 2 to 5 have similar components to Layer 1, but each layer is optimized according to the characteristics of the data being processed.
The simulation results for each layer are as follows:
-
Layer 5 Simulation Result
The implementation result is as follows:
The DSD_MNIST_Streamline project successfully implements an efficient digital signal processing system through its five-layer structure. The simulation and implementation results for each layer validate the system's performance. This project demonstrates high performance and efficiency in processing the MNIST dataset.
For additional inquiries, please contact us at:
- Email: opqrs0422@naver.com
- GitHub: GitHub Profile