Merge pull request stm32duino#2235 from fpistm/STM32CubeG0_update

chore(G0): update to latest STM32CubeG0 v1.6.2
fpistm · Jan 2, 2024 · c117c7e · c117c7e
2 parents 17ca401 + 213ec65
commit c117c7e
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Showing 127 changed files with 4,307 additions and 3,133 deletions.
diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g030xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g030xx.h
@@ -4045,6 +4045,12 @@ typedef struct
 #define RCC_CFGR_SWS_1                 (0x2UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000010 */
 #define RCC_CFGR_SWS_2                 (0x4UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000020 */
 
+#define RCC_CFGR_SWS_HSISYS            (0x00000000UL)                          /*!< HSISYS used as system clock */
+#define RCC_CFGR_SWS_HSE               (0x00000008UL)                          /*!< HSE used as system clock */
+#define RCC_CFGR_SWS_PLLRCLK           (0x00000010UL)                          /*!< PLLRCLK used as system clock */
+#define RCC_CFGR_SWS_LSI               (0x00000018UL)                          /*!< LSI used as system clock */
+#define RCC_CFGR_SWS_LSE               (0x00000100UL)                          /*!< LSE used as system clock */
+
 /*!< HPRE configuration */
 #define RCC_CFGR_HPRE_Pos              (8U)
 #define RCC_CFGR_HPRE_Msk              (0xFUL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000F00 */

diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h
@@ -4225,6 +4225,12 @@ typedef struct
 #define RCC_CFGR_SWS_1                 (0x2UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000010 */
 #define RCC_CFGR_SWS_2                 (0x4UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000020 */
 
+#define RCC_CFGR_SWS_HSISYS            (0x00000000UL)                          /*!< HSISYS used as system clock */
+#define RCC_CFGR_SWS_HSE               (0x00000008UL)                          /*!< HSE used as system clock */
+#define RCC_CFGR_SWS_PLLRCLK           (0x00000010UL)                          /*!< PLLRCLK used as system clock */
+#define RCC_CFGR_SWS_LSI               (0x00000018UL)                          /*!< LSI used as system clock */
+#define RCC_CFGR_SWS_LSE               (0x00000100UL)                          /*!< LSE used as system clock */
+
 /*!< HPRE configuration */
 #define RCC_CFGR_HPRE_Pos              (8U)
 #define RCC_CFGR_HPRE_Msk              (0xFUL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000F00 */

diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g041xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g041xx.h
@@ -4461,6 +4461,12 @@ typedef struct
 #define RCC_CFGR_SWS_1                 (0x2UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000010 */
 #define RCC_CFGR_SWS_2                 (0x4UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000020 */
 
+#define RCC_CFGR_SWS_HSISYS            (0x00000000UL)                          /*!< HSISYS used as system clock */
+#define RCC_CFGR_SWS_HSE               (0x00000008UL)                          /*!< HSE used as system clock */
+#define RCC_CFGR_SWS_PLLRCLK           (0x00000010UL)                          /*!< PLLRCLK used as system clock */
+#define RCC_CFGR_SWS_LSI               (0x00000018UL)                          /*!< LSI used as system clock */
+#define RCC_CFGR_SWS_LSE               (0x00000100UL)                          /*!< LSE used as system clock */
+
 /*!< HPRE configuration */
 #define RCC_CFGR_HPRE_Pos              (8U)
 #define RCC_CFGR_HPRE_Msk              (0xFUL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000F00 */

diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g050xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g050xx.h
@@ -4064,6 +4064,12 @@ typedef struct
 #define RCC_CFGR_SWS_1                 (0x2UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000010 */
 #define RCC_CFGR_SWS_2                 (0x4UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000020 */
 
+#define RCC_CFGR_SWS_HSISYS            (0x00000000UL)                          /*!< HSISYS used as system clock */
+#define RCC_CFGR_SWS_HSE               (0x00000008UL)                          /*!< HSE used as system clock */
+#define RCC_CFGR_SWS_PLLRCLK           (0x00000010UL)                          /*!< PLLRCLK used as system clock */
+#define RCC_CFGR_SWS_LSI               (0x00000018UL)                          /*!< LSI used as system clock */
+#define RCC_CFGR_SWS_LSE               (0x00000100UL)                          /*!< LSE used as system clock */
+
 /*!< HPRE configuration */
 #define RCC_CFGR_HPRE_Pos              (8U)
 #define RCC_CFGR_HPRE_Msk              (0xFUL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000F00 */

diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g051xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g051xx.h
@@ -4561,6 +4561,12 @@ typedef struct
 #define RCC_CFGR_SWS_1                 (0x2UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000010 */
 #define RCC_CFGR_SWS_2                 (0x4UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000020 */
 
+#define RCC_CFGR_SWS_HSISYS            (0x00000000UL)                          /*!< HSISYS used as system clock */
+#define RCC_CFGR_SWS_HSE               (0x00000008UL)                          /*!< HSE used as system clock */
+#define RCC_CFGR_SWS_PLLRCLK           (0x00000010UL)                          /*!< PLLRCLK used as system clock */
+#define RCC_CFGR_SWS_LSI               (0x00000018UL)                          /*!< LSI used as system clock */
+#define RCC_CFGR_SWS_LSE               (0x00000100UL)                          /*!< LSE used as system clock */
+
 /*!< HPRE configuration */
 #define RCC_CFGR_HPRE_Pos              (8U)
 #define RCC_CFGR_HPRE_Msk              (0xFUL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000F00 */

diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g061xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g061xx.h
@@ -4797,6 +4797,12 @@ typedef struct
 #define RCC_CFGR_SWS_1                 (0x2UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000010 */
 #define RCC_CFGR_SWS_2                 (0x4UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000020 */
 
+#define RCC_CFGR_SWS_HSISYS            (0x00000000UL)                          /*!< HSISYS used as system clock */
+#define RCC_CFGR_SWS_HSE               (0x00000008UL)                          /*!< HSE used as system clock */
+#define RCC_CFGR_SWS_PLLRCLK           (0x00000010UL)                          /*!< PLLRCLK used as system clock */
+#define RCC_CFGR_SWS_LSI               (0x00000018UL)                          /*!< LSI used as system clock */
+#define RCC_CFGR_SWS_LSE               (0x00000100UL)                          /*!< LSE used as system clock */
+
 /*!< HPRE configuration */
 #define RCC_CFGR_HPRE_Pos              (8U)
 #define RCC_CFGR_HPRE_Msk              (0xFUL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000F00 */

diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g070xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g070xx.h
@@ -4193,6 +4193,12 @@ typedef struct
 #define RCC_CFGR_SWS_1                 (0x2UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000010 */
 #define RCC_CFGR_SWS_2                 (0x4UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000020 */
 
+#define RCC_CFGR_SWS_HSISYS            (0x00000000UL)                          /*!< HSISYS used as system clock */
+#define RCC_CFGR_SWS_HSE               (0x00000008UL)                          /*!< HSE used as system clock */
+#define RCC_CFGR_SWS_PLLRCLK           (0x00000010UL)                          /*!< PLLRCLK used as system clock */
+#define RCC_CFGR_SWS_LSI               (0x00000018UL)                          /*!< LSI used as system clock */
+#define RCC_CFGR_SWS_LSE               (0x00000100UL)                          /*!< LSE used as system clock */
+
 /*!< HPRE configuration */
 #define RCC_CFGR_HPRE_Pos              (8U)
 #define RCC_CFGR_HPRE_Msk              (0xFUL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000F00 */

diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g071xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g071xx.h
@@ -4896,6 +4896,12 @@ typedef struct
 #define RCC_CFGR_SWS_1                 (0x2UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000010 */
 #define RCC_CFGR_SWS_2                 (0x4UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000020 */
 
+#define RCC_CFGR_SWS_HSISYS            (0x00000000UL)                          /*!< HSISYS used as system clock */
+#define RCC_CFGR_SWS_HSE               (0x00000008UL)                          /*!< HSE used as system clock */
+#define RCC_CFGR_SWS_PLLRCLK           (0x00000010UL)                          /*!< PLLRCLK used as system clock */
+#define RCC_CFGR_SWS_LSI               (0x00000018UL)                          /*!< LSI used as system clock */
+#define RCC_CFGR_SWS_LSE               (0x00000100UL)                          /*!< LSE used as system clock */
+
 /*!< HPRE configuration */
 #define RCC_CFGR_HPRE_Pos              (8U)
 #define RCC_CFGR_HPRE_Msk              (0xFUL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000F00 */

diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g081xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g081xx.h
@@ -5132,6 +5132,12 @@ typedef struct
 #define RCC_CFGR_SWS_1                 (0x2UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000010 */
 #define RCC_CFGR_SWS_2                 (0x4UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000020 */
 
+#define RCC_CFGR_SWS_HSISYS            (0x00000000UL)                          /*!< HSISYS used as system clock */
+#define RCC_CFGR_SWS_HSE               (0x00000008UL)                          /*!< HSE used as system clock */
+#define RCC_CFGR_SWS_PLLRCLK           (0x00000010UL)                          /*!< PLLRCLK used as system clock */
+#define RCC_CFGR_SWS_LSI               (0x00000018UL)                          /*!< LSI used as system clock */
+#define RCC_CFGR_SWS_LSE               (0x00000100UL)                          /*!< LSE used as system clock */
+
 /*!< HPRE configuration */
 #define RCC_CFGR_HPRE_Pos              (8U)
 #define RCC_CFGR_HPRE_Msk              (0xFUL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000F00 */

diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b0xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b0xx.h
@@ -325,7 +325,7 @@ typedef struct
 typedef struct
 {
   __IO uint32_t CR1;          /*!< PWR Power Control Register 1,                     Address offset: 0x00 */
-       uint32_t RESERVED0;    /*!< Reserved,                                         Address offset: 0x04 */
+  __IO uint32_t CR2;          /*!< PWR Power Control Register 2,                     Address offset: 0x04 */
   __IO uint32_t CR3;          /*!< PWR Power Control Register 3,                     Address offset: 0x08 */
   __IO uint32_t CR4;          /*!< PWR Power Control Register 4,                     Address offset: 0x0C */
   __IO uint32_t SR1;          /*!< PWR Power Status Register 1,                      Address offset: 0x10 */
@@ -4363,6 +4363,9 @@ typedef struct
 #define PWR_CR1_LPR_Msk           (0x1UL << PWR_CR1_LPR_Pos)                   /*!< 0x00004000 */
 #define PWR_CR1_LPR               PWR_CR1_LPR_Msk                              /*!< Regulator Low-Power Run mode */
 
+#define PWR_CR2_USV_Pos           (10U)
+#define PWR_CR2_USV_Msk           (0x1UL << PWR_CR2_USV_Pos)                   /*!< 0x00000400 */
+#define PWR_CR2_USV               PWR_CR2_USV_Msk                              /*!< VDD USB Supply Valid */
 
 /********************  Bit definition for PWR_CR3 register  ********************/
 #define PWR_CR3_EWUP_Pos          (0U)
@@ -5162,6 +5165,12 @@ typedef struct
 #define RCC_CFGR_SWS_1                 (0x2UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000010 */
 #define RCC_CFGR_SWS_2                 (0x4UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000020 */
 
+#define RCC_CFGR_SWS_HSISYS            (0x00000000UL)                          /*!< HSISYS used as system clock */
+#define RCC_CFGR_SWS_HSE               (0x00000008UL)                          /*!< HSE used as system clock */
+#define RCC_CFGR_SWS_PLLRCLK           (0x00000010UL)                          /*!< PLLRCLK used as system clock */
+#define RCC_CFGR_SWS_LSI               (0x00000018UL)                          /*!< LSI used as system clock */
+#define RCC_CFGR_SWS_LSE               (0x00000100UL)                          /*!< LSE used as system clock */
+
 /*!< HPRE configuration */
 #define RCC_CFGR_HPRE_Pos              (8U)
 #define RCC_CFGR_HPRE_Msk              (0xFUL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000F00 */

diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h
@@ -6146,6 +6146,12 @@ typedef struct
 #define RCC_CFGR_SWS_1                 (0x2UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000010 */
 #define RCC_CFGR_SWS_2                 (0x4UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000020 */
 
+#define RCC_CFGR_SWS_HSISYS            (0x00000000UL)                          /*!< HSISYS used as system clock */
+#define RCC_CFGR_SWS_HSE               (0x00000008UL)                          /*!< HSE used as system clock */
+#define RCC_CFGR_SWS_PLLRCLK           (0x00000010UL)                          /*!< PLLRCLK used as system clock */
+#define RCC_CFGR_SWS_LSI               (0x00000018UL)                          /*!< LSI used as system clock */
+#define RCC_CFGR_SWS_LSE               (0x00000100UL)                          /*!< LSE used as system clock */
+
 /*!< HPRE configuration */
 #define RCC_CFGR_HPRE_Pos              (8U)
 #define RCC_CFGR_HPRE_Msk              (0xFUL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000F00 */

diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0c1xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0c1xx.h
@@ -6382,6 +6382,12 @@ typedef struct
 #define RCC_CFGR_SWS_1                 (0x2UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000010 */
 #define RCC_CFGR_SWS_2                 (0x4UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000020 */
 
+#define RCC_CFGR_SWS_HSISYS            (0x00000000UL)                          /*!< HSISYS used as system clock */
+#define RCC_CFGR_SWS_HSE               (0x00000008UL)                          /*!< HSE used as system clock */
+#define RCC_CFGR_SWS_PLLRCLK           (0x00000010UL)                          /*!< PLLRCLK used as system clock */
+#define RCC_CFGR_SWS_LSI               (0x00000018UL)                          /*!< LSI used as system clock */
+#define RCC_CFGR_SWS_LSE               (0x00000100UL)                          /*!< LSE used as system clock */
+
 /*!< HPRE configuration */
 #define RCC_CFGR_HPRE_Pos              (8U)
 #define RCC_CFGR_HPRE_Msk              (0xFUL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000F00 */

diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h
@@ -90,7 +90,7 @@
   */
 #define __STM32G0_CMSIS_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
 #define __STM32G0_CMSIS_VERSION_SUB1   (0x04U) /*!< [23:16] sub1 version */
-#define __STM32G0_CMSIS_VERSION_SUB2   (0x03U) /*!< [15:8]  sub2 version */
+#define __STM32G0_CMSIS_VERSION_SUB2   (0x04U) /*!< [15:8]  sub2 version */
 #define __STM32G0_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
 #define __STM32G0_CMSIS_VERSION        ((__STM32G0_CMSIS_VERSION_MAIN << 24)\
                                        |(__STM32G0_CMSIS_VERSION_SUB1 << 16)\

diff --git a/...vers/CMSIS/Device/ST/STM32G0xx/License.md → ...vers/CMSIS/Device/ST/STM32G0xx/LICENSE.md b/...vers/CMSIS/Device/ST/STM32G0xx/License.md → ...vers/CMSIS/Device/ST/STM32G0xx/LICENSE.md
diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/README.md b/system/Drivers/CMSIS/Device/ST/STM32G0xx/README.md
@@ -1,19 +1,21 @@
 # STM32CubeG0 CMSIS Device MCU Component
 
+![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/cmsis_device_g0.svg?color=brightgreen)
+
 ## Overview
 
 **STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost.
 
-**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform, delivered for each STM32 series.
-   * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product
-   * The STM32 HAL-LL drivers : an abstraction drivers layer, the API ensuring maximized portability across the STM32 portfolio
-   * The BSP Drivers of each evaluation or demonstration board provided by this STM32 series
-   * A consistent set of middlewares components such as RTOS, USB, FatFS, Graphics, STM32_TouchSensing_Library ...
-   * A full set of software projects (basic examples, applications or demonstrations) for each board provided by this STM32 series
+**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform delivered for each STM32 series.
+   * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product.
+   * The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio.
+   * The BSP drivers of each evaluation, demonstration or nucleo board provided for this STM32 series.
+   * A consistent set of middleware libraries such as RTOS, USB, FatFS, graphics, touch sensing library...
+   * A full set of software projects (basic examples, applications, and demonstrations) for each board provided for this STM32 series.
 
-Two models of publication are proposed for the STM32Cube embedded software :
-   * The monolithic **MCU Package** : all STM32Cube software modules of one STM32 series are present (Drivers, Middlewares, Projects, Utilities) in the repo (usual name **STM32Cubexx**, xx corresponding to the STM32 series)
-   * The **MCU component** : progressively from November 2019, each STM32Cube software module being part of the STM32Cube MCU Package, will be delivered as an individual repo, allowing the user to select and get only the required software functions.
+Two models of publication are proposed for the STM32Cube embedded software:
+   * The monolithic **MCU Package**: all STM32Cube software modules of one STM32 series are present (Drivers, Middleware, Projects, Utilities) in the repository (usual name **STM32Cubexx**, xx corresponding to the STM32 series).
+   * The **MCU component**: each STM32Cube software module being part of the STM32Cube MCU Package, is delivered as an individual repository, allowing the user to select and get only the required software functions.
 
 ## Description
 
@@ -30,6 +32,5 @@ It is **crucial** that you use a consistent set of versions for the CMSIS Core -
 The full **STM32CubeG0** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeG0).
 
 ## Troubleshooting
-If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/cmsis_device_g0/issues/new).
 
-For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).
+Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide.