From 39e47864dbc07eafe052cd4e8547d200415eca34 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 3 Dec 2024 15:05:55 +0100 Subject: [PATCH 1/3] system(U0) update STM32U0xx HAL Drivers to v1.2.0 Included in STM32CubeU0 FW v1.2.0 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 63 ++++++++++++--- .../Inc/stm32u0xx_hal_pcd.h | 8 ++ .../Inc/stm32u0xx_hal_pcd_ex.h | 1 - .../Inc/stm32u0xx_hal_rcc.h | 2 +- .../Inc/stm32u0xx_ll_usb.h | 39 +++++---- .../Inc/stm32u0xx_ll_utils.h | 1 + .../STM32U0xx_HAL_Driver/Release_Notes.html | 50 ++++++++++-- .../STM32U0xx_HAL_Driver/Src/stm32u0xx_hal.c | 2 +- .../Src/stm32u0xx_hal_i2c.c | 79 +++++++++++++------ .../Src/stm32u0xx_hal_pcd.c | 41 ++++++---- .../Src/stm32u0xx_hal_pcd_ex.c | 2 - .../Src/stm32u0xx_hal_timebase_tim_template.c | 69 +++++++++------- .../Src/stm32u0xx_hal_uart.c | 4 +- .../Src/stm32u0xx_ll_usb.c | 73 ++++++++--------- .../Src/stm32u0xx_ll_utils.c | 5 ++ .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 16 files changed, 290 insertions(+), 151 deletions(-) diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32U0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 0d7e9cf34b..afaa855825 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32U0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -472,7 +472,9 @@ extern "C" { #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) #define PAGESIZE FLASH_PAGE_SIZE +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */ #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD @@ -601,6 +603,15 @@ extern "C" { #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ +#if defined(STM32U5) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection +#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection + +#endif /* STM32U5 */ + #if defined(STM32H5) #define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC #define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC @@ -875,6 +886,10 @@ extern "C" { #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE +#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7) +#define HRTIMInterruptResquests HRTIMInterruptRequests +#endif /* STM32F3 || STM32G4 || STM32H7 */ + #if defined(STM32G4) #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable @@ -1012,8 +1027,8 @@ extern "C" { #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) - #endif /* STM32F3 */ + /** * @} */ @@ -1264,10 +1279,10 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 -#if defined(STM32H5) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM -#endif /* STM32H5 || STM32H7RS */ +#endif /* STM32H5 || STM32H7RS || STM32N6 */ #if defined(STM32WBA) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE @@ -1279,10 +1294,10 @@ extern "C" { #define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL #endif /* STM32WBA */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ #if defined(STM32F7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK @@ -1466,7 +1481,7 @@ extern "C" { #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 #endif -#if defined(STM32U5) || defined(STM32MP2) +#if defined(STM32U5) #define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS #define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK #endif @@ -2014,12 +2029,12 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose * @{ */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey #define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock #define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock #define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ /** * @} @@ -3680,7 +3695,7 @@ extern "C" { #endif #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0) + defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3931,7 +3946,8 @@ extern "C" { */ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) + defined (STM32WBA) || defined (STM32V7) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || \ + defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -4225,6 +4241,33 @@ extern "C" { #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +#if defined(STM32U5) +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM +#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT +#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0 +#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1 +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM +#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID +#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0 +#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1 +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK +#endif /** * @} */ diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_pcd.h b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_pcd.h index b2fe0973ed..e0a9c8da97 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_pcd.h +++ b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_pcd.h @@ -462,6 +462,14 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); #define PCD_SET_BULK_EP_DBUF PCD_SET_EP_KIND #define PCD_CLEAR_BULK_EP_DBUF PCD_CLEAR_EP_KIND +/** + * @brief Sets/clears directly STATUS_OUT bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_OUT_STATUS USB_DRD_SET_CHEP_KIND +#define PCD_CLEAR_OUT_STATUS USB_DRD_CLEAR_CHEP_KIND /** * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_pcd_ex.h b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_pcd_ex.h index 0a36580a53..141a0838e1 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_pcd_ex.h +++ b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_pcd_ex.h @@ -47,7 +47,6 @@ extern "C" { */ - HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress); diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_rcc.h b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_rcc.h index 8a7be48930..7a76870a8e 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_rcc.h +++ b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_rcc.h @@ -619,7 +619,7 @@ typedef struct */ /* Flags in the CR register */ #define RCC_FLAG_MSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos)) /*!< MSI Ready flag */ -#define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIDY_Pos)) /*!< HSI Ready flag */ +#define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< HSI Ready flag */ #define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< HSE Ready flag */ #define RCC_FLAG_PLLRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL Ready flag */ diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_usb.h b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_usb.h index a467f73c93..2beeb65b37 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_usb.h +++ b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_usb.h @@ -53,26 +53,26 @@ typedef enum */ typedef struct { - uint32_t dev_endpoints; /*!< Device Endpoints number. + uint8_t dev_endpoints; /*!< Device Endpoints number. This parameter depends on the used USB core. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - uint32_t speed; /*!< USB Core speed. - This parameter can be any value of @ref PCD_Speed/HCD_Speed - (HCD_SPEED_xxx, HCD_SPEED_xxx) */ + uint8_t speed; /*!< USB Core speed. + This parameter can be any value of @ref PCD_Speed/HCD_Speed + (HCD_SPEED_xxx, HCD_SPEED_xxx) */ - uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ + uint8_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ - uint32_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ + uint8_t phy_itface; /*!< Select the used PHY interface. + This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ - uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ + uint8_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ - uint32_t low_power_enable; /*!< Enable or disable the low Power Mode. */ + uint8_t low_power_enable; /*!< Enable or disable the low Power Mode. */ - uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */ + uint8_t lpm_enable; /*!< Enable or disable Link Power Management. */ - uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ + uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */ } USB_CfgTypeDef; typedef struct @@ -526,20 +526,17 @@ typedef USB_EPTypeDef USB_DRD_EPTypeDef; \ (pdwReg) &= ~(USB_CNTRX_BLSIZE | USB_CNTRX_NBLK_MSK); \ \ - if ((wCount) > 62U) \ + if ((wCount) == 0U) \ { \ - USB_DRD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ + (pdwReg) |= USB_CNTRX_BLSIZE; \ + } \ + else if ((wCount) <= 62U) \ + { \ + USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ } \ else \ { \ - if ((wCount) == 0U) \ - { \ - (pdwReg) |= USB_CNTRX_BLSIZE; \ - } \ - else \ - { \ - USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ - } \ + USB_DRD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ } \ } while(0) /* USB_DRD_SET_CHEP_CNT_RX_REG */ diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_utils.h b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_utils.h index b22934c2ed..1cd9ecbacb 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_utils.h +++ b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_utils.h @@ -294,6 +294,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency); /** * @} diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32U0xx_HAL_Driver/Release_Notes.html index 156268ff8b..5d84d76cc0 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32U0xx_HAL_Driver/Release_Notes.html @@ -40,11 +40,45 @@

Purpose

Update History

- +

Main Changes

-

Maintenance release of HAL and LL drivers for STM32U083 / STM32U073 / STM32U031 devices

+

Second maintenance release of HAL and LL drivers for STM32U083 / STM32U073 / STM32U031 devices

Contents

+

HAL and LL driver second maintenance release

+
    +
  • HAL drivers: +
      +
    • HAL UART driver: +
        +
      • Fix DMA Rx abort procedure impact on ongoing UART Tx transfer in polling mode.
        • +
      • +
    • HAL RCC driver: +
        +
      • Minors implementation enhancements.
        • +
      • +
    • LL UTILS driver: +
        +
      • Add LL_SetFlashLatency API based on a call of UTILS_SetFlashLatency.
        • +
      • +
    • +
+

Known Limitations

+
    +
  • None
    • +
+

Backward Compatibility

+
    +
  • Not applicable
    • +
+
+
+
+ +
+

Main Changes

+

Maintenance release of HAL and LL drivers for STM32U083 / STM32U073 / STM32U031 devices

+

Contents

HAL and LL driver maintenance release

  • HAL drivers: @@ -67,11 +101,11 @@

    Contents

-

Known Limitations

+

Known Limitations

  • None
-

Backward Compatibility

+

Backward Compatibility

  • Not applicable
@@ -80,19 +114,19 @@

Backward Compatibility

-

Main Changes

+

Main Changes

First official release of HAL and LL drivers for STM32U083 / STM32U073 / STM32U031 devices

-

Contents

+

Contents

HAL and LL driver beta version for all peripherals

  • HAL: ADC, CORTEX, COMP, CRC, CRYP, DAC, DMA, EXTI, GPIO, I2C, I2S, IRDA, IWDG, LPTIM, OPAMP, LTDC, PCD, PWR, RCC, RNG, RTC, SMARTCARD, SPI, TIM, UART, USART, WWDG

  • LL: ADC, COMP, CRC, CRS, DAC, DMA, EXTI, GPIO, I2C, LPTIM, LPUART, OPAMP, PWR, RCC, RNG, RTC, SPI, TIM, USART, USB, UTILS

-

Known Limitations

+

Known Limitations

  • None
-

Backward Compatibility

+

Backward Compatibility

  • Not applicable
diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal.c b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal.c index dc48e79e7e..1b8961257e 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal.c +++ b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal.c @@ -55,7 +55,7 @@ * @brief STM32U0xx HAL Driver version number */ #define __STM32U0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32U0xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */ +#define __STM32U0xx_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ #define __STM32U0xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32U0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32U0xx_HAL_VERSION ((__STM32U0xx_HAL_VERSION_MAIN << 24U)\ diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_i2c.c b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_i2c.c index 6b9c8690ba..efa40a4cce 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_i2c.c +++ b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_i2c.c @@ -3220,6 +3220,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __IO uint32_t I2C_Trials = 0UL; + HAL_StatusTypeDef status = HAL_OK; + FlagStatus tmp1; FlagStatus tmp2; @@ -3277,37 +3279,64 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Wait until STOPF flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_ERROR; + /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */ + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Reset the error code for next trial */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + status = HAL_ERROR; + } } + else + { + /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */ - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Device is ready */ - hi2c->State = HAL_I2C_STATE_READY; + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_OK; + return HAL_OK; + } } else { - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } + /* A non acknowledge is detected, this mean that device not respond to its address, + a new trial must be performed */ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Clear STOP Flag, auto generated with autoend*/ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + status = HAL_ERROR; + } + else + { + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } } /* Increment Trials */ I2C_Trials++; + + if ((I2C_Trials < Trials) && (status == HAL_ERROR)) + { + status = HAL_OK; + } + } while (I2C_Trials < Trials); /* Update I2C state */ @@ -6263,7 +6292,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* Increment Buffer pointer */ hi2c->pBuffPtr++; - if ((hi2c->XferSize > 0U)) + if (hi2c->XferSize > 0U) { hi2c->XferSize--; hi2c->XferCount--; @@ -6419,7 +6448,7 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* Increment Buffer pointer */ hi2c->pBuffPtr++; - if ((hi2c->XferSize > 0U)) + if (hi2c->XferSize > 0U) { hi2c->XferSize--; hi2c->XferCount--; @@ -6873,7 +6902,7 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) + if (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -6913,7 +6942,7 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -6952,7 +6981,7 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -7030,7 +7059,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK)) { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -7197,15 +7226,17 @@ static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t T static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { + uint32_t tmp; + /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); /* Declaration of tmp to prevent undefined behavior of volatile usage */ - uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ - (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); /* update CR2 register */ MODIFY_REG(hi2c->Instance->CR2, \ diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_pcd.c b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_pcd.c index 61b42db81f..0341786d8b 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_pcd.c +++ b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_pcd.c @@ -1389,7 +1389,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { - HAL_StatusTypeDef ret = HAL_OK; + HAL_StatusTypeDef ret = HAL_OK; PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) @@ -1404,7 +1404,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, } ep->num = ep_addr & EP_ADDR_MSK; - ep->maxpacket = ep_mps; + ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; ep->type = ep_type; /* Set initial data PID. */ @@ -1809,7 +1809,6 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID)) { - PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); } } @@ -1930,7 +1929,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* Manage Single Buffer Transaction */ if ((wEPVal & USB_EP_KIND) == 0U) { - /* multi-packet on the NON control IN endpoint */ + /* Multi-packet on the NON control IN endpoint */ TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); if (ep->xfer_len > TxPctSize) @@ -2006,7 +2005,7 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, if (ep->xfer_len == 0U) { - /* set NAK to OUT endpoint since double buffer is enabled */ + /* Set NAK to OUT endpoint since double buffer is enabled */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); } @@ -2038,11 +2037,11 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, if (ep->xfer_len == 0U) { - /* set NAK on the current endpoint */ + /* Set NAK on the current endpoint */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); } - /*Need to FreeUser Buffer*/ + /* Need to FreeUser Buffer */ if ((wEPVal & USB_EP_DTOG_TX) == 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); @@ -2092,6 +2091,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + if (ep->type == EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -2103,10 +2108,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); } + + return HAL_OK; } else /* Transfer is not yet Done */ { - /* need to Free USB Buff */ + /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) != 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); @@ -2137,7 +2144,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, } /* Write remaining Data to Buffer */ - /* Set the Double buffer counter for pma buffer1 */ + /* Set the Double buffer counter for pma buffer0 */ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len); /* Copy user buffer to USB PMA */ @@ -2165,6 +2172,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + if (ep->type == EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -2177,10 +2190,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); } + + return HAL_OK; } else /* Transfer is not yet Done */ { - /* need to Free USB Buff */ + /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) == 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); @@ -2210,7 +2225,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, ep->xfer_fill_db = 0; } - /* Set the Double buffer counter for pmabuffer1 */ + /* Set the Double buffer counter for pma buffer1 */ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); /* Copy the user buffer to USB PMA */ @@ -2219,7 +2234,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, } } - /*enable endpoint IN*/ + /* Enable endpoint IN */ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); return HAL_OK; @@ -2227,13 +2242,11 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - /** * @} */ #endif /* defined (USB_DRD_FS) */ #endif /* HAL_PCD_MODULE_ENABLED */ - /** * @} */ diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_pcd_ex.c b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_pcd_ex.c index cb66616f11..42b6ac0b64 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_pcd_ex.c +++ b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_pcd_ex.c @@ -242,7 +242,6 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) } } - /** * @brief Activate LPM feature. * @param hpcd PCD handle @@ -279,7 +278,6 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) } - /** * @brief Send LPM message to user layer callback. * @param hpcd PCD handle diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_timebase_tim_template.c b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_timebase_tim_template.c index aed8fe44bc..fe6e04cc06 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_timebase_tim_template.c +++ b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_timebase_tim_template.c @@ -53,14 +53,14 @@ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -extern TIM_HandleTypeDef TimHandle; -TIM_HandleTypeDef TimHandle; +static TIM_HandleTypeDef TimHandle; + /* Private function prototypes -----------------------------------------------*/ -void TIM6_DAC_LPTIM1_IRQHandler(void); +void TIM16_IRQHandler(void); /* Private functions ---------------------------------------------------------*/ /** - * @brief This function configures the TIM6 as a time base source. + * @brief This function configures the TIM16 as a time base source. * The time source is configured to have 1ms time base with a dedicated * Tick interrupt priority. * @note This function is called automatically at the beginning of program after @@ -75,15 +75,10 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) uint32_t uwAPB1Prescaler; uint32_t uwPrescalerValue; uint32_t pFLatency; + HAL_StatusTypeDef status; - /*Configure the TIM6 IRQ priority */ - HAL_NVIC_SetPriority(TIM6_DAC_LPTIM1_IRQn, TickPriority, 0U); - - /* Enable the TIM6 global Interrupt */ - HAL_NVIC_EnableIRQ(TIM6_DAC_LPTIM1_IRQn); - - /* Enable TIM6 clock */ - __HAL_RCC_TIM6_CLK_ENABLE(); + /* Enable TIM16 clock */ + __HAL_RCC_TIM16_CLK_ENABLE(); /* Get clock configuration */ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); @@ -91,7 +86,7 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) /* Get APB1 prescaler */ uwAPB1Prescaler = clkconfig.APB1CLKDivider; - /* Compute TIM6 clock */ + /* Compute TIM16 clock */ if (uwAPB1Prescaler == RCC_HCLK_DIV1) { uwTimclock = HAL_RCC_GetPCLK1Freq(); @@ -101,14 +96,14 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) uwTimclock = 2U * HAL_RCC_GetPCLK1Freq(); } - /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */ + /* Compute the prescaler value to have TIM16 counter clock equal to 1MHz */ uwPrescalerValue = (uint32_t)((uwTimclock / 1000000U) - 1U); - /* Initialize TIM6 */ - TimHandle.Instance = TIM6; + /* Initialize TIM16 */ + TimHandle.Instance = TIM16; /* Initialize TIMx peripheral as follow: - + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base. + + Period = [(TIM16CLK/1000) - 1]. to have a (1/1000) s time base. + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + ClockDivision = 0 + Counter direction = Up @@ -117,42 +112,59 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) TimHandle.Init.Prescaler = uwPrescalerValue; TimHandle.Init.ClockDivision = 0U; TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP; - TimHandle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - if (HAL_TIM_Base_Init(&TimHandle) == HAL_OK) + + status = HAL_TIM_Base_Init(&TimHandle); + if (status == HAL_OK) { /* Start the TIM time Base generation in interrupt mode */ - return HAL_TIM_Base_Start_IT(&TimHandle); + status = HAL_TIM_Base_Start_IT(&TimHandle); + if (status == HAL_OK) + { + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + /* Enable the TIM16 global Interrupt */ + HAL_NVIC_SetPriority(TIM16_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + status = HAL_ERROR; + } + } } - /* Return function status */ - return HAL_ERROR; + /* Enable the TIM16 global Interrupt */ + HAL_NVIC_EnableIRQ(TIM16_IRQn); + + /* Return function status */ + return status; } /** * @brief Suspend Tick increment. - * @note Disable the tick increment by disabling TIM6 update interrupt. + * @note Disable the tick increment by disabling TIM16 update interrupt. * @retval None */ void HAL_SuspendTick(void) { - /* Disable TIM6 update interrupt */ + /* Disable TIM16 update interrupt */ __HAL_TIM_DISABLE_IT(&TimHandle, TIM_IT_UPDATE); } /** * @brief Resume Tick increment. - * @note Enable the tick increment by enabling TIM6 update interrupt. + * @note Enable the tick increment by enabling TIM16 update interrupt. * @retval None */ void HAL_ResumeTick(void) { - /* Enable TIM6 update interrupt */ + /* Enable TIM16 update interrupt */ __HAL_TIM_ENABLE_IT(&TimHandle, TIM_IT_UPDATE); } /** * @brief Period elapsed callback in non blocking mode - * @note This function is called when TIM6 interrupt took place, inside + * @note This function is called when TIM16 interrupt took place, inside * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment * a global variable "uwTick" used as application time base. * @param htim TIM handle @@ -165,9 +177,10 @@ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) /** * @brief This function handles TIM interrupt request. + * @param None * @retval None */ -void TIM6_DAC_LPTIM1_IRQHandler(void) +void TIM16_IRQHandler(void) { HAL_TIM_IRQHandler(&TimHandle); } diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_uart.c b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_uart.c index 88a274288f..6618689f90 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_uart.c +++ b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_uart.c @@ -1080,6 +1080,9 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) reception services: (+) HAL_UARTEx_RxEventCallback() + (#) Wakeup from Stop mode Callback: + (+) HAL_UARTEx_WakeupCallback() + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is @@ -3880,7 +3883,6 @@ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); huart->RxXferCount = 0U; - huart->TxXferCount = 0U; #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_ll_usb.c b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_ll_usb.c index 1c84370e4b..d23da79bbf 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_ll_usb.c +++ b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_ll_usb.c @@ -344,6 +344,10 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); + /* Set endpoint RX count */ + PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); + + /* Set endpoint RX to valid state */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); } @@ -448,7 +452,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) /* IN endpoint */ if (ep->is_in == 1U) { - /*Multi packet transfer*/ + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { len = ep->maxpacket; @@ -550,9 +554,9 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); } } - else /* manage isochronous double buffer IN mode */ + else /* Manage isochronous double buffer IN mode */ { - /* each Time to write in PMA xfer_len_db will */ + /* Each Time to write in PMA xfer_len_db will */ ep->xfer_len_db -= len; /* Fill the data buffer */ @@ -584,19 +588,25 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) { if (ep->doublebuffer == 0U) { + if ((ep->xfer_len == 0U) && (ep->type == EP_TYPE_CTRL)) + { + /* This is a status out stage set the OUT_STATUS */ + PCD_SET_OUT_STATUS(USBx, ep->num); + } + else + { + PCD_CLEAR_OUT_STATUS(USBx, ep->num); + } + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { - len = ep->maxpacket; - ep->xfer_len -= len; + ep->xfer_len -= ep->maxpacket; } else { - len = ep->xfer_len; ep->xfer_len = 0U; } - /* configure and validate Rx endpoint */ - PCD_SET_EP_RX_CNT(USBx, ep->num, len); } #if (USE_USB_DOUBLE_BUFFER == 1U) else @@ -605,15 +615,13 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) /* Set the Double buffer counter */ if (ep->type == EP_TYPE_BULK) { - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); - /* Coming from ISR */ if (ep->xfer_count != 0U) { - /* update last value to check if there is blocking state */ + /* Update last value to check if there is blocking state */ wEPVal = (uint16_t)PCD_GET_ENDPOINT(USBx, ep->num); - /*Blocking State */ + /* Blocking State */ if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) { @@ -624,18 +632,8 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) /* iso out double */ else if (ep->type == EP_TYPE_ISOC) { - /* Multi packet transfer */ - if (ep->xfer_len > ep->maxpacket) - { - len = ep->maxpacket; - ep->xfer_len -= len; - } - else - { - len = ep->xfer_len; - ep->xfer_len = 0U; - } - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len); + /* Only single packet transfer supported in FS */ + ep->xfer_len = 0U; } else { @@ -679,26 +677,23 @@ HAL_StatusTypeDef USB_EPSetStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) */ HAL_StatusTypeDef USB_EPClearStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) { - if (ep->doublebuffer == 0U) + if (ep->is_in != 0U) { - if (ep->is_in != 0U) - { - PCD_CLEAR_TX_DTOG(USBx, ep->num); + PCD_CLEAR_TX_DTOG(USBx, ep->num); - if (ep->type != EP_TYPE_ISOC) - { - /* Configure NAK status for the Endpoint */ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); - } - } - else + if (ep->type != EP_TYPE_ISOC) { - PCD_CLEAR_RX_DTOG(USBx, ep->num); - - /* Configure VALID status for the Endpoint */ - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); } } + else + { + PCD_CLEAR_RX_DTOG(USBx, ep->num); + + /* Configure VALID status for the Endpoint */ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + } return HAL_OK; } diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_ll_utils.c b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_ll_utils.c index 11c6718e91..3743cb55af 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_ll_utils.c +++ b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_ll_utils.c @@ -558,6 +558,11 @@ static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency) return status; } +ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency) +{ + return UTILS_SetFlashLatency(HCLK_Frequency); +} + /** * @brief Function to check that PLL can be modified * @param PLL_InputFrequency PLL input frequency (in Hz) diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 3b963a2342..e701797f82 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -16,7 +16,7 @@ * STM32L4: 1.13.5 * STM32L5: 1.0.6 * STM32MP1: 1.6.0 - * STM32U0: 1.1.0 + * STM32U0: 1.2.0 * STM32U5: 1.6.0 * STM32WB: 1.14.3 * STM32WBA: 1.4.0 From 6d0d9561a174cd481b550e8425c8d4683abf7712 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 3 Dec 2024 15:05:55 +0100 Subject: [PATCH 2/3] system(U0): update STM32U0xx CMSIS Drivers to v1.2.0 Included in STM32CubeU0 FW v1.2.0 Signed-off-by: Frederic Pillon --- .../Device/ST/STM32U0xx/Include/stm32u031xx.h | 4 ++++ .../Device/ST/STM32U0xx/Include/stm32u073xx.h | 4 ++++ .../Device/ST/STM32U0xx/Include/stm32u083xx.h | 4 ++++ .../Device/ST/STM32U0xx/Include/stm32u0xx.h | 12 +++++----- .../Device/ST/STM32U0xx/Release_Notes.html | 23 +++++++++++++++---- .../Source/Templates/system_stm32u0xx.c | 2 +- .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 7 files changed, 39 insertions(+), 12 deletions(-) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u031xx.h b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u031xx.h index 342d2d408b..30773e1225 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u031xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u031xx.h @@ -706,6 +706,10 @@ typedef struct #define UID_BASE (0x1FFF3E50UL) /*!< Unique device ID register base address */ #define FLASHSIZE_BASE (0x1FFF3EA0UL) /*!< Flash size data register base address */ +/*!< Bootloader Firmware */ +/************ Bootloader Exit Secure Memory Firmware *************/ +#define BL_EXIT_SEC_MEM_BASE (0x1FFF3500UL) + /** * @} */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u073xx.h b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u073xx.h index e3d494d543..0d969053e4 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u073xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u073xx.h @@ -775,6 +775,10 @@ typedef struct #define UID_BASE (0x1FFF6E50UL) /*!< Unique device ID register base address */ #define FLASHSIZE_BASE (0x1FFF6EA0UL) /*!< Flash size data register base address */ +/*!< Bootloader Firmware */ +/************ Bootloader Exit Secure Memory Firmware *************/ +#define BL_EXIT_SEC_MEM_BASE (0x1FFF6000UL) + /** * @} */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u083xx.h b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u083xx.h index c7da4e5ffb..4c092084e7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u083xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u083xx.h @@ -809,6 +809,10 @@ typedef struct #define UID_BASE (0x1FFF6E50UL) /*!< Unique device ID register base address */ #define FLASHSIZE_BASE (0x1FFF6EA0UL) /*!< Flash size data register base address */ +/*!< Bootloader Firmware */ +/************ Bootloader Exit Secure Memory Firmware *************/ +#define BL_EXIT_SEC_MEM_BASE (0x1FFF6000UL) + /** * @} */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u0xx.h b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u0xx.h index 836da3fdb7..fceae34817 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u0xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u0xx.h @@ -8,8 +8,8 @@ * is using in the C source code, usually in main.c. This file contains: * - Configuration section that allows to select: * - The STM32U0xx device used in the target application - * - To use or not the peripheral’s drivers in application code(i.e. - * code will be based on direct access to peripheral’s registers + * - To use or not the peripheral's drivers in application code(i.e. + * code will be based on direct access to peripheral's registers * rather than drivers API), this option is controlled by * "#define USE_HAL_DRIVER" * @@ -76,10 +76,10 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number 1.0.0 + * @brief CMSIS Device version number 1.2.0 */ #define __STM32U0_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32U0_CMSIS_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __STM32U0_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ #define __STM32U0_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32U0_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32U0_CMSIS_VERSION ((__STM32U0_CMSIS_VERSION_MAIN << 24)\ @@ -127,8 +127,8 @@ typedef enum typedef enum { - ERROR = 0, - SUCCESS = !ERROR + SUCCESS = 0, + ERROR = !SUCCESS } ErrorStatus; /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Release_Notes.html index 4f916bc6cf..d59b66c2a0 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Release_Notes.html @@ -30,27 +30,42 @@

Release Notes for  STM32U0xx C

Update History

- +

Main Changes

  • CMSIS Device Maintenance Release version of bits and registers definition aligned with the RM0503 (STM32U0 reference manual).
      +
    • Fixed the right CFGR_HPRE shift in the SystemCoreClockUpdate API.
      • +
    • Align the ErrorStatus typedef declaration with HAL_StatusTypeDef.
      • +
    • Add the address to use for the bootloader jump service.
      • +
    • +
+

+
+
+
+ +
+

Main Changes

+
    +
  • CMSIS Device Maintenance Release version of bits and registers definition aligned with the RM0503 (STM32U0 reference manual). +
    • Add I2C_CR1_SBC bit definition.
    • Removed the I2C_CR1_SWRST bit definition.
-

+

-

Main Changes

+

Main Changes

  • First official release version of bits and registers definition aligned with the RM0503 (STM32U0 reference manual).
-

+

diff --git a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/system_stm32u0xx.c b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/system_stm32u0xx.c index 3d01a3cfbf..ab4b081111 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/system_stm32u0xx.c +++ b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/system_stm32u0xx.c @@ -327,7 +327,7 @@ void SystemCoreClockUpdate(void) } /* Compute HCLK clock frequency --------------------------------------------*/ /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U) & 0xFU]; + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos) & 0xFU]; /* HCLK clock frequency */ SystemCoreClock >>= tmp; } diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 4cc65c8401..9f902c90db 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -16,7 +16,7 @@ * STM32L4: 1.7.4 * STM32L5: 1.0.6 * STM32MP1: 1.6.0 - * STM32U0: 1.0.0 + * STM32U0: 1.2.0 * STM32U5: 1.4.0 * STM32WB: 1.12.2 * STM32WBA: 1.4.0 From f671ecf42d14ee06ff76cf7723a4b96ae052b68a Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 3 Dec 2024 15:15:52 +0100 Subject: [PATCH 3/3] chore(U0): update variants against CubeMX DB release 6.0.130 Signed-off-by: Frederic Pillon --- variants/STM32U0xx/U031C(6-8)(T-U)/PeripheralPins.c | 2 +- variants/STM32U0xx/U031F(4-6-8)P/PeripheralPins.c | 2 +- variants/STM32U0xx/U031G(6-8)Y/PeripheralPins.c | 2 +- variants/STM32U0xx/U031K(4-6-8)U/PeripheralPins.c | 2 +- variants/STM32U0xx/U031R(6-8)(I-T)/PeripheralPins.c | 2 +- .../STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)/PeripheralPins.c | 2 +- variants/STM32U0xx/U073H(8-B-C)Y_U083HCY/PeripheralPins.c | 2 +- variants/STM32U0xx/U073K(8-B-C)U_U083KCU/PeripheralPins.c | 2 +- variants/STM32U0xx/U073M(8-B-C)I_U083MCI/PeripheralPins.c | 2 +- variants/STM32U0xx/U073M(8-B-C)T_U083MCT/PeripheralPins.c | 2 +- .../STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T)/PeripheralPins.c | 2 +- 11 files changed, 11 insertions(+), 11 deletions(-) diff --git a/variants/STM32U0xx/U031C(6-8)(T-U)/PeripheralPins.c b/variants/STM32U0xx/U031C(6-8)(T-U)/PeripheralPins.c index 8139f2df39..bbcd077193 100644 --- a/variants/STM32U0xx/U031C(6-8)(T-U)/PeripheralPins.c +++ b/variants/STM32U0xx/U031C(6-8)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U031C6Tx.xml, STM32U031C6Ux.xml * STM32U031C8Tx.xml, STM32U031C8Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U031F(4-6-8)P/PeripheralPins.c b/variants/STM32U0xx/U031F(4-6-8)P/PeripheralPins.c index 910afaeee4..c0d26545a9 100644 --- a/variants/STM32U0xx/U031F(4-6-8)P/PeripheralPins.c +++ b/variants/STM32U0xx/U031F(4-6-8)P/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U031F4Px.xml, STM32U031F6Px.xml * STM32U031F8Px.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U031G(6-8)Y/PeripheralPins.c b/variants/STM32U0xx/U031G(6-8)Y/PeripheralPins.c index 62ce1874de..5f4c81356b 100644 --- a/variants/STM32U0xx/U031G(6-8)Y/PeripheralPins.c +++ b/variants/STM32U0xx/U031G(6-8)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U031G6Yx.xml, STM32U031G8Yx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U031K(4-6-8)U/PeripheralPins.c b/variants/STM32U0xx/U031K(4-6-8)U/PeripheralPins.c index 5a68d3d7c5..3eb2d757b8 100644 --- a/variants/STM32U0xx/U031K(4-6-8)U/PeripheralPins.c +++ b/variants/STM32U0xx/U031K(4-6-8)U/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U031K4Ux.xml, STM32U031K6Ux.xml * STM32U031K8Ux.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U031R(6-8)(I-T)/PeripheralPins.c b/variants/STM32U0xx/U031R(6-8)(I-T)/PeripheralPins.c index 7b64347cb9..af55e3797f 100644 --- a/variants/STM32U0xx/U031R(6-8)(I-T)/PeripheralPins.c +++ b/variants/STM32U0xx/U031R(6-8)(I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U031R6Ix.xml, STM32U031R6Tx.xml * STM32U031R8Ix.xml, STM32U031R8Tx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)/PeripheralPins.c b/variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)/PeripheralPins.c index 1421817484..b0cbb2806f 100644 --- a/variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)/PeripheralPins.c +++ b/variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32U073CBTx.xml, STM32U073CBUx.xml * STM32U073CCTx.xml, STM32U073CCUx.xml * STM32U083CCTx.xml, STM32U083CCUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U073H(8-B-C)Y_U083HCY/PeripheralPins.c b/variants/STM32U0xx/U073H(8-B-C)Y_U083HCY/PeripheralPins.c index f4b5cb0f02..c6b61ba6e9 100644 --- a/variants/STM32U0xx/U073H(8-B-C)Y_U083HCY/PeripheralPins.c +++ b/variants/STM32U0xx/U073H(8-B-C)Y_U083HCY/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U073H8Yx.xml, STM32U073HBYx.xml * STM32U073HCYx.xml, STM32U083HCYx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U073K(8-B-C)U_U083KCU/PeripheralPins.c b/variants/STM32U0xx/U073K(8-B-C)U_U083KCU/PeripheralPins.c index b43617fe59..fc44d4504d 100644 --- a/variants/STM32U0xx/U073K(8-B-C)U_U083KCU/PeripheralPins.c +++ b/variants/STM32U0xx/U073K(8-B-C)U_U083KCU/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U073K8Ux.xml, STM32U073KBUx.xml * STM32U073KCUx.xml, STM32U083KCUx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U073M(8-B-C)I_U083MCI/PeripheralPins.c b/variants/STM32U0xx/U073M(8-B-C)I_U083MCI/PeripheralPins.c index c8488fc360..6dc6fa1841 100644 --- a/variants/STM32U0xx/U073M(8-B-C)I_U083MCI/PeripheralPins.c +++ b/variants/STM32U0xx/U073M(8-B-C)I_U083MCI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U073M8Ix.xml, STM32U073MBIx.xml * STM32U073MCIx.xml, STM32U083MCIx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U073M(8-B-C)T_U083MCT/PeripheralPins.c b/variants/STM32U0xx/U073M(8-B-C)T_U083MCT/PeripheralPins.c index 64db7f4623..68d8910556 100644 --- a/variants/STM32U0xx/U073M(8-B-C)T_U083MCT/PeripheralPins.c +++ b/variants/STM32U0xx/U073M(8-B-C)T_U083MCT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U073M8Tx.xml, STM32U073MBTx.xml * STM32U073MCTx.xml, STM32U083MCTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T)/PeripheralPins.c b/variants/STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T)/PeripheralPins.c index a68200a729..29391f2991 100644 --- a/variants/STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T)/PeripheralPins.c +++ b/variants/STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32U073RBIx.xml, STM32U073RBTx.xml * STM32U073RCIx.xml, STM32U073RCTx.xml * STM32U083RCIx.xml, STM32U083RCTx.xml - * CubeMX DB release 6.0.120 + * CubeMX DB release 6.0.130 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h"