CPU.hdl

/**
 * The Hack CPU (Central Processing unit), consisting of an ALU,
 * two registers named A and D, and a program counter named PC.
 * The CPU is designed to fetch and execute instructions written in 
 * the Hack machine language. In particular, functions as follows:
 * Executes the inputted instruction according to the Hack machine 
 * language specification. The D and A in the language specification
 * refer to CPU-resident registers, while M refers to the external
 * memory location addressed by A, i.e. to Memory[A]. The inM input 
 * holds the value of this location. If the current instruction needs 
 * to write a value to M, the value is placed in outM, the address 
 * of the target location is placed in the addressM output, and the 
 * writeM control bit is asserted. (When writeM==0, any value may 
 * appear in outM). The outM and writeM outputs are combinational: 
 * they are affected instantaneously by the execution of the current 
 * instruction. The addressM and pc outputs are clocked: although they 
 * are affected by the execution of the current instruction, they commit 
 * to their new values only in the next time step. If reset==1 then the 
 * CPU jumps to address 0 (i.e. pc is set to 0 in next time step) rather 
 * than to the address resulting from executing the current instruction. 
 */

CHIP CPU {
    IN  inM[16],         // M value input  (M = contents of RAM[A])
        instruction[16], // Instruction for execution
        reset;           // Signals whether to re-start the current
                         // program (reset==1) or continue executing
                         // the current program (reset==0).

    OUT outM[16],        // M value output
        writeM,          // Write to M? 
        addressM[15],    // Address in data memory (of M)
        pc[15];          // address of next instruction

    PARTS:
    Mux16(a=instruction, b=outALU, sel=instruction[15], out=outMux1);
    And(a=instruction[3], b=instruction[15], out=writeM);
    And(a=instruction[4], b=instruction[15], out=writeD);
    And(a=instruction[5], b=instruction[15], out=insWriteA);
    Not(in=instruction[15], out=addWriteA);
    Or(a=insWriteA, b=addWriteA, out=writeA);
    ARegister(in=outMux1, load=writeA, out[0..14]=addressM, out=outRegA);
    Mux16(a=outRegA, b=inM, sel=instruction[12], out=outMux2);
    DRegister(in=outALU, load=writeD, out=outRegD);
    ALU(x=outRegD, y=outMux2, zx=instruction[11], nx=instruction[10], zy=instruction[9], ny=instruction[8], f=instruction[7], no=instruction[6], out=outALU, out=outM, zr=zero, ng=negative);
    Not(in=zero, out=notZero);
    Not(in=negative, out=notNegative);
    And(a=notZero, b=notNegative, out=positive);
    And(a=instruction[0], b=instruction[15], out=insJumpPos);
    And(a=instruction[1], b=instruction[15], out=insJumpZero);
    And(a=instruction[2], b=instruction[15], out=insJumpNeg);
    And(a=insJumpPos, b=positive, out=jumpPos);
    And(a=insJumpZero, b=zero, out=jumpZero);
    And(a=insJumpNeg, b=negative, out=jumpNeg);
    Or(a=jumpPos, b=jumpZero, out=jump1);
    Or(a=jump1, b=jumpNeg, out=jump2);
    Not(in=jump2, out=notJump2);
    PC(in=outRegA, load=jump2, inc=notJump2, reset=reset, out[0..14]=pc);
}