interrupt_and_exception_handling.txt

mtvec: [1:0]  MODE: Vectored or Direct
       [31:2] BASE: Interrupt Vector Base Address

        In direct mode all traps will set the PC to BASE
        In vectoed mode pc will be set to BASE+4*cause.

mcause: [30:0] Exception Code(WLRL): Code indicating what caused the traps
        [31:31] Interrupt: Indicates if it was an interrupt or some other Exception.

Important Note: Environment calls seem to set mepc to the instruction address which actually called ecall. Which means,
that the SW handler has to advance the address manually by 4. For "asynchronous interrupts" it seems, that this is done by the HW. 
Which means, that depending on source of the trap we need to advance the mepc by for or not. I am still not sure if this behavior is only
for ecall/ebreak or also all other non asynchronous interrupts.

Interrupt | Exception Code | Description:
    1     |       0        |    User software interrupt
    1     |       1        |    Supervisor software interrupt
    1     |       2        |    Reserved
    1     |       3        |    Machine software interrupt
    1     |       4        |    User timer interrupt
    1     |       5        |    Supervisor timer interrupt
    1     |       6        |    Reserved
    1     |       7        |    Machine timer interrupt
    1     |       8        |    User external interrupt
    1     |       9        |    Supervisor external interrupt
    1     |       10       |    Reserved
    1     |       11       |    Machine external interrupt
    1     |       ≥1       |    2 Reserved
    0     |       0        |    Instruction address misaligned
    0     |       1        |    Instruction access fault
    0     |       2        |    Illegal instruction
    0     |       3        |    Breakpoint
    0     |       4        |    Load address misaligned
    0     |       5        |    Load access fault
    0     |       6        |    Store/AMO address misaligned
    0     |       7        |    Store/AMO access fault
    0     |       8        |    Environment call from U-mode
    0     |       9        |    Environment call from S-mode
    0     |       10       |    Reserved
    0     |       11       |    Environment call from M-mode
    0     |       12       |    Instruction page fault
    0     |       13       |    Load page fault
    0     |       14       |    Reserved
    0     |       15       |    Store/AMO page fault
    0     |       ≥1       |    6 Reserved

mepc: 
    When a trap is taken into M-mode, mepc is written with the virtual address of the instruction that
    encountered the exception. Otherwise, mepc is never written by the implementation, though it may
    be explicitly written by software.

    - Means: FPGA has to set the mepc to the instruction which caused the trap, when an interrupt or ecall 
    is triggered. The ISR in software has to set the mepc register to the instruction causing the trap + 4 
    and call mret (or using gcc attribute: void __attribute__ ((interrupt)) ) to return from the exception handler.