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- test: riscv_rand_instr_test
description: >
Random instruction stress test
iterations: 1
gen_test: riscv_instr_base_test
gen_opts: >
+instr_cnt=100
+no_data_page=1
+num_of_sub_program=0
+bare_program_mode=1
+directed_instr_0=riscv_load_store_rand_instr_stream,50
+directed_instr_1=riscv_load_store_hazard_instr_stream,50
+directed_instr_2=riscv_int_numeric_corner_stream,50
+directed_instr_3=riscv_single_load_store_instr_stream,20
+directed_instr_4=riscv_jal_instr,20
+directed_instr_5=riscv_load_store_stress_instr_stream,20
rtl_test: core_base_test
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Answered by
kkmonk
Feb 24, 2022
Replies: 1 comment
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I solved this problem by removing redundant assignment in riscv-instr.py |
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Answer selected by
kkmonk
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I solved this problem by removing redundant assignment in riscv-instr.py