facedancer: disable hyperram until it's landed in luna-soc

cynthion/python/src/gateware/facedancer/top.py

@@ -1,5 +1,5 @@
 #
-# This file is part of LUNA.
+# This file is part of Cynthion.
 #
 # Copyright (c) 2020-2024 Great Scott Gadgets <info@greatscottgadgets.com>
 # SPDX-License-Identifier: BSD-3-Clause
@@ -18,7 +18,7 @@
 
 from luna.gateware.utils.cdc         import synchronize
 
-from luna_soc.gateware.core          import blockram, psram, spiflash, timer, uart, usb2
+from luna_soc.gateware.core          import blockram, spiflash, timer, uart, usb2
 from luna_soc.gateware.core.spiflash import ECP5ConfigurationFlashInterface, SPIPHYController
 from luna_soc.gateware.cpu           import InterruptController, VexRiscv
 from luna_soc.gateware.provider      import cynthion as provider
@@ -127,8 +127,8 @@ def __init__(self, clock_frequency_hz, domain="sync"):
         self.wb_decoder.add(self.spiflash.bus, addr=self.spiflash_base, name="spiflash")
 
         # hyperram
-        self.hyperram = psram.Peripheral(size=self.hyperram_size)
-        self.wb_decoder.add(self.hyperram.bus, addr=self.hyperram_base, name="hyperram")
+        # TODO self.hyperram = psram.Peripheral(size=self.hyperram_size)
+        # TODO self.wb_decoder.add(self.hyperram.bus, addr=self.hyperram_base, name="hyperram")
 
         # csr decoder
         self.csr_decoder = csr.Decoder(addr_width=28, data_width=8)
@@ -247,7 +247,7 @@ def elaborate(self, platform):
         m.submodules += self.blockram
 
         # hyperram
-        m.submodules += self.hyperram
+        # TODO m.submodules += self.hyperram
 
         # spiflash
         m.submodules += [self.spiflash_provider, self.spiflash, self.spiflash_bus, self.spiflash_phy]

firmware/memory.x

@@ -1,6 +1,6 @@
 MEMORY {
-    spiflash : ORIGIN = 0x100b0000, LENGTH = 0x00400000
     blockram : ORIGIN = 0x00000000, LENGTH = 0x00010000
+    spiflash : ORIGIN = 0x100b0000, LENGTH = 0x00400000
 }
 
 REGION_ALIAS("REGION_TEXT",   spiflash);