From b2cc6f0c88102dcc21483e2b50d8864de2b2b009 Mon Sep 17 00:00:00 2001 From: Erik Zachrisson Date: Thu, 26 Dec 2013 18:52:56 +0100 Subject: [PATCH 01/13] Fix missing apostrophe --- rigol.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rigol.py b/rigol.py index 6b5bfbd..f2897fc 100755 --- a/rigol.py +++ b/rigol.py @@ -27,7 +27,7 @@ RAW_DATA_LENGTH = 9000 class RigolScope(Scope): - '''Class to control a Rigol DS1000 series oscilloscope'' + '''Class to control a Rigol DS1000 series oscilloscope''' def __init__(self, device): '''Initialize Hardware''' try: From 9b4e7fc8b6d3fe3453309df6092c50cf6eaa0357 Mon Sep 17 00:00:00 2001 From: Erik Zachrisson Date: Thu, 26 Dec 2013 19:26:22 +0100 Subject: [PATCH 02/13] Point to default usbtmc for now as this works better --- rigol.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rigol.py b/rigol.py index f2897fc..33c4e80 100755 --- a/rigol.py +++ b/rigol.py @@ -188,7 +188,7 @@ def forceTrigger(self): if __name__ == "__main__": print "# RigolScope Test #" - scope = RigolScope("/dev/usbtmc-rigol") + scope = RigolScope("/dev/usbtmc0") scope.grabData() scope.writeWaveformToFile("out.dat") scope.close() From 4a89436accb125cfbeba5ce4bb71fd8b1836dc32 Mon Sep 17 00:00:00 2001 From: Erik Zachrisson Date: Thu, 26 Dec 2013 19:35:05 +0100 Subject: [PATCH 03/13] Update udev rules --- README | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/README b/README index dc5c52e..9dfa423 100644 --- a/README +++ b/README @@ -28,7 +28,7 @@ matplotlib Setup USB permissions for udev ------------------------------ -echo 'ACTION=="add", BUS=="usb", SYSFS{idVendor}=="1ab1", SYSFS{idProduct}=="0588", GROUP:="adm"' > tmpfile +echo 'ACTION=="add", BUS=="usb", ATTR{idVendor}=="1ab1", ATTR{idProduct}=="0588", GROUP:="adm"' > tmpfile sudo chown root:root tmpfile sudo mv tmpfile /etc/udev/rules.d/10-rigol.rules sudo udevadm control --reload-rules @@ -40,6 +40,6 @@ On my DS1102E the WAVE:POINT:MODE options seem to have no effect. Maybe the fir udev can add more symlinks with SYMLINK+="usbtmc-newname" new udev rules -ACTION=="add", BUS=="usb", SYSFS{idVendor}=="164e", SYSFS{idProduct}=="0fa2", GROUP:="adm", SYMLINK+="usbtmc-bnc645" -ACTION=="add", BUS=="usb", SYSFS{idVendor}=="1ab1", SYSFS{idProduct}=="0588", GROUP:="adm", SYMLINK+="usbtmc-rigol" +ACTION=="add", BUS=="usb", ATTR{idVendor}=="164e", ATTR{idProduct}=="0fa2", GROUP:="adm", SYMLINK+="usbtmc-bnc645" +ACTION=="add", BUS=="usb", ATTR{idVendor}=="1ab1", ATTR{idProduct}=="0588", GROUP:="adm", SYMLINK+="usbtmc-rigol" From 1e8f2c38cd83d23ad86ca898da9f6c7f7012da55 Mon Sep 17 00:00:00 2001 From: Erik Zachrisson Date: Thu, 26 Dec 2013 19:35:42 +0100 Subject: [PATCH 04/13] Adjust paths and module name --- tests/get_data.py | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/tests/get_data.py b/tests/get_data.py index 0acdfdd..73b94ba 100755 --- a/tests/get_data.py +++ b/tests/get_data.py @@ -9,14 +9,12 @@ import sys import os from matplotlib import pyplot -sys.path.append(os.path.expanduser('~/Source')) -sys.path.append(os.path.expanduser('~/src')) -sys.path.append('/var/local/src') -from pyoscope import RigolScope -from pyoscope import Waverunner -from pyoscope import makeDataFilePath +sys.path.append(os.path.expanduser('.')) +from oscope import RigolScope +from oscope import Waverunner +from oscope import makeDataFilePath """ Capture data from Rigol oscilloscope and write to a file - usage: python save_channel.py + usage: python get_data.py if filename is not given STDOUT will be used""" SCOPE_ADDRESS = 'nigpib1' From c75882cf46b8397b9d299196db2aba753c7a979e Mon Sep 17 00:00:00 2001 From: Erik Zachrisson Date: Thu, 26 Dec 2013 19:42:28 +0100 Subject: [PATCH 05/13] Fixup module imports --- tests/get_data.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/tests/get_data.py b/tests/get_data.py index 73b94ba..9b57b97 100755 --- a/tests/get_data.py +++ b/tests/get_data.py @@ -10,9 +10,9 @@ import os from matplotlib import pyplot sys.path.append(os.path.expanduser('.')) -from oscope import RigolScope -from oscope import Waverunner -from oscope import makeDataFilePath +from rigol import RigolScope +from waverunner import Waverunner +from utils import makeDataFilePath """ Capture data from Rigol oscilloscope and write to a file usage: python get_data.py if filename is not given STDOUT will be used""" @@ -29,8 +29,8 @@ sys.exit(1) print filename -#scope = RigolScope("/dev/usbtmc0") -scope = Waverunner(SCOPE_ADDRESS) +scope = RigolScope("/dev/usbtmc0") +#scope = Waverunner(SCOPE_ADDRESS) scope.grabData() scope.writeWaveformToFile(filename) scope.close() From cdb209ad1bbf09ef34e98af4b4262b743a394312 Mon Sep 17 00:00:00 2001 From: Erik Zachrisson Date: Thu, 26 Dec 2013 19:47:41 +0100 Subject: [PATCH 06/13] Import RigolScope from rigol module. Source /dev/usbtmc0 --- tests/display_rigol.py | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/tests/display_rigol.py b/tests/display_rigol.py index 5032430..b2abd32 100755 --- a/tests/display_rigol.py +++ b/tests/display_rigol.py @@ -13,13 +13,11 @@ from matplotlib import pyplot import sys import os -sys.path.append(os.path.expanduser('~/Source')) -sys.path.append(os.path.expanduser('~/src')) -sys.path.append('/var/local/src') -from pyoscope import RigolScope +sys.path.append(os.path.expanduser('.')) +from rigol import RigolScope # Initialize our scope -scope = RigolScope("/dev/usbtmc-rigol") +scope = RigolScope("/dev/usbtmc0") scope.grabData() data1 = scope.getScaledWaveform(1) data2 = scope.getScaledWaveform(2) From fe1cc65b724919099f439cd5d4f2dd73c51fdd12 Mon Sep 17 00:00:00 2001 From: Erik Zachrisson Date: Thu, 26 Dec 2013 19:51:34 +0100 Subject: [PATCH 07/13] Add newline --- __init__.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/__init__.py b/__init__.py index dc8bfbf..868bdba 100644 --- a/__init__.py +++ b/__init__.py @@ -1,4 +1,5 @@ from oscope import * from rigol import RigolScope from waverunner import Waverunner -from utils import * \ No newline at end of file +from utils import * + From ad0b772cf978d61bacc73aed43c39717f06c6315 Mon Sep 17 00:00:00 2001 From: Erik Zachrisson Date: Thu, 26 Dec 2013 19:54:23 +0100 Subject: [PATCH 08/13] Unlock scope after use --- tests/display_rigol.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/display_rigol.py b/tests/display_rigol.py index b2abd32..a94b801 100755 --- a/tests/display_rigol.py +++ b/tests/display_rigol.py @@ -35,7 +35,7 @@ else: tUnit = "S" -# close interface +scope.unlock() scope.close() # Plot the data From 1e72337a553edf537407bf262719f2a1d9b15a38 Mon Sep 17 00:00:00 2001 From: Erik Zachrisson Date: Thu, 26 Dec 2013 19:55:45 +0100 Subject: [PATCH 09/13] Unlock scope after use --- tests/get_data.py | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/get_data.py b/tests/get_data.py index 9b57b97..0b91bda 100755 --- a/tests/get_data.py +++ b/tests/get_data.py @@ -33,5 +33,6 @@ #scope = Waverunner(SCOPE_ADDRESS) scope.grabData() scope.writeWaveformToFile(filename) +scope.unlock() scope.close() From f19a0fd665b0de1c5ad772a28c70ff52491acfc0 Mon Sep 17 00:00:00 2001 From: Erik Zachrisson Date: Thu, 26 Dec 2013 19:58:24 +0100 Subject: [PATCH 10/13] Remove superfluous paths. Import correct module --- tests/display_wr.py | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/tests/display_wr.py b/tests/display_wr.py index d7fde98..a7a3075 100755 --- a/tests/display_wr.py +++ b/tests/display_wr.py @@ -13,10 +13,8 @@ from matplotlib import pyplot import sys import os -sys.path.append(os.path.expanduser('~/Source')) -sys.path.append(os.path.expanduser('~/src')) -sys.path.append('/var/local/src') -from pyoscope import Waverunner +sys.path.append(os.path.expanduser('.')) +from waverunner import Waverunner """ Example program to plot the Y-T data from one scope channel derived from capture_channel_1.py but using new interface methods """ From 3c7854de5545769a151f0dfae2f72de1337aa2b1 Mon Sep 17 00:00:00 2001 From: Erik Zachrisson Date: Thu, 26 Dec 2013 20:00:51 +0100 Subject: [PATCH 11/13] Source correct paths and modules --- tests/realtime_plot_demo.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/tests/realtime_plot_demo.py b/tests/realtime_plot_demo.py index b15d955..36e0567 100755 --- a/tests/realtime_plot_demo.py +++ b/tests/realtime_plot_demo.py @@ -14,7 +14,10 @@ ''' import numpy from matplotlib import pyplot -from pyusbtmc import RigolScope +import sys +import os +sys.path.append(os.path.expanduser('.')) +from rigol import RigolScope import time # Initialize our scope From ce5ac2311730f1701ae311c1a09be1fee618435d Mon Sep 17 00:00:00 2001 From: niun Date: Thu, 4 Sep 2014 13:28:33 +0200 Subject: [PATCH 12/13] replace udev BUS with SUBSYSTEM BUS was removed somewhere after udev version 149. It can be replaced by SUBSYSTEM. Source: http://sdrblog.wordpress.com/2010/02/01/new-udev-rules/ --- README | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/README b/README index 9dfa423..2e97aaf 100644 --- a/README +++ b/README @@ -28,8 +28,9 @@ matplotlib Setup USB permissions for udev ------------------------------ -echo 'ACTION=="add", BUS=="usb", ATTR{idVendor}=="1ab1", ATTR{idProduct}=="0588", GROUP:="adm"' > tmpfile +echo 'ACTION=="add", SUBSYSTEM=="usb", ATTR{idVendor}=="1ab1", ATTR{idProduct}=="0588", GROUP:="adm"' > tmpfile sudo chown root:root tmpfile +sudo chmod 644 tmpfile sudo mv tmpfile /etc/udev/rules.d/10-rigol.rules sudo udevadm control --reload-rules @@ -40,6 +41,6 @@ On my DS1102E the WAVE:POINT:MODE options seem to have no effect. Maybe the fir udev can add more symlinks with SYMLINK+="usbtmc-newname" new udev rules -ACTION=="add", BUS=="usb", ATTR{idVendor}=="164e", ATTR{idProduct}=="0fa2", GROUP:="adm", SYMLINK+="usbtmc-bnc645" -ACTION=="add", BUS=="usb", ATTR{idVendor}=="1ab1", ATTR{idProduct}=="0588", GROUP:="adm", SYMLINK+="usbtmc-rigol" +ACTION=="add", SUBSYSTEM=="usb", ATTR{idVendor}=="164e", ATTR{idProduct}=="0fa2", GROUP:="adm", SYMLINK+="usbtmc-bnc645" +ACTION=="add", SUBSYSTEM=="usb", ATTR{idVendor}=="1ab1", ATTR{idProduct}=="0588", GROUP:="adm", SYMLINK+="usbtmc-rigol" From 1bb862ddb68f95fad010d2328c6f695714911f68 Mon Sep 17 00:00:00 2001 From: niun Date: Thu, 4 Sep 2014 15:19:41 +0200 Subject: [PATCH 13/13] udev looks for parent's ATTRS to match child When matching against ATTR, udev will match the raw usb node directly, but we want to modify the device that is using the usbtmc driver (the toplevel child /dev/usbtmc0). This will be matched, when matching against parents ATTRS and SUBSYSTEMS. --- README | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/README b/README index 2e97aaf..3e321e9 100644 --- a/README +++ b/README @@ -28,7 +28,7 @@ matplotlib Setup USB permissions for udev ------------------------------ -echo 'ACTION=="add", SUBSYSTEM=="usb", ATTR{idVendor}=="1ab1", ATTR{idProduct}=="0588", GROUP:="adm"' > tmpfile +echo 'ACTION=="add", SUBSYSTEMS=="usb", ATTRS{idVendor}=="1ab1", ATTRS{idProduct}=="0588", GROUP="adm"' > tmpfile sudo chown root:root tmpfile sudo chmod 644 tmpfile sudo mv tmpfile /etc/udev/rules.d/10-rigol.rules @@ -41,6 +41,6 @@ On my DS1102E the WAVE:POINT:MODE options seem to have no effect. Maybe the fir udev can add more symlinks with SYMLINK+="usbtmc-newname" new udev rules -ACTION=="add", SUBSYSTEM=="usb", ATTR{idVendor}=="164e", ATTR{idProduct}=="0fa2", GROUP:="adm", SYMLINK+="usbtmc-bnc645" -ACTION=="add", SUBSYSTEM=="usb", ATTR{idVendor}=="1ab1", ATTR{idProduct}=="0588", GROUP:="adm", SYMLINK+="usbtmc-rigol" +ACTION=="add", SUBSYSTEMS=="usb", ATTRS{idVendor}=="164e", ATTRS{idProduct}=="0fa2", GROUP:="adm", SYMLINK+="usbtmc-bnc645" +ACTION=="add", SUBSYSTEMS=="usb", ATTRS{idVendor}=="1ab1", ATTRS{idProduct}=="0588", GROUP:="adm", SYMLINK+="usbtmc-rigol"