diff --git a/Firmware/Firmware.ATXMEGA/SoundCard/app.c b/Firmware/Firmware.ATXMEGA/SoundCard/app.c index df377c2..e4cc170 100644 --- a/Firmware/Firmware.ATXMEGA/SoundCard/app.c +++ b/Firmware/Firmware.ATXMEGA/SoundCard/app.c @@ -22,7 +22,7 @@ extern bool (*app_func_wr_pointer[])(void*); /************************************************************************/ static const uint8_t default_device_name[] = "SoundCard"; -#define MAJOR_FW_VERSION 2 +#define MAJOR_FW_VERSION 3 void hwbp_app_initialize(void) { @@ -30,7 +30,7 @@ void hwbp_app_initialize(void) uint8_t hwH = 2; uint8_t hwL = 2; uint8_t fwH = MAJOR_FW_VERSION; - uint8_t fwL = 2; + uint8_t fwL = 0; uint8_t ass = 0; /* Start core */ @@ -158,9 +158,31 @@ void core_callback_initialize_hardware(void) ADCA_CH0_CTRL |= ADC_CH_START_bm; // Force the first conversion while(!(ADCA_CH0_INTFLAGS & ADC_CH_CHIF_bm)); // Wait for conversion to finish ADCA_CH0_INTFLAGS = ADC_CH_CHIF_bm; // Clear interrupt bit + + ADCA_CH0_INTCTRL |= ADC_CH_INTLVL_LO_gc; // Enable ADC0 interrupt } -void core_callback_reset_registers(void) {} +void core_callback_reset_registers(void) +{ + app_regs.REG_DI0_CONF = GM_DI_SYNC; + app_regs.REG_DI1_CONF = GM_DI_SYNC; + + app_regs.REG_DI0_SOUND_INDEX = 2000; // 2 KHz + app_regs.REG_DI1_SOUND_INDEX = 4000; // 4 KHz + app_regs.REG_DI0_ATTENUATION_LEFT = 60; // -6 DFS + app_regs.REG_DI1_ATTENUATION_LEFT = 60; // -6 DFS + app_regs.REG_DI0_ATTENUATION_RIGHT = 60; // -6 DFS + app_regs.REG_DI1_ATTENUATION_RIGHT = 60; // -6 DFS + + app_regs.REG_DO0_CONF = GM_DO_PULSE; + app_regs.REG_DO1_CONF = GM_DO_DIG; + app_regs.REG_DO2_CONF = GM_DO_DIG; + + app_regs.REG_DATA_STREAM_CONF = GM_DATA_STREAM_OFF; + + app_regs.REG_ADC0_CONF = GM_ADC0_PURE_ANALOG_INPUT; + app_regs.REG_ADC1_CONF = GM_ADC1_PURE_ANALOG_INPUT; +} void core_callback_registers_were_reinitialized(void) {} @@ -181,41 +203,42 @@ void core_callback_visualen_to_off(void) /************************************************************************/ /* Callbacks: Change on the operation mode */ /************************************************************************/ -void core_callback_device_to_standby(void) {} +extern uint16_t last_sound_triggered; + +void core_callback_device_to_standby(void) +{ + par_cmd_stop(); + last_sound_triggered = 0; +} void core_callback_device_to_active(void) {} -void core_callback_device_to_enchanced_active(void) {} +void core_callback_device_to_enhanced_active(void) {} void core_callback_device_to_speed(void) {} /************************************************************************/ /* Callbacks: 1 ms timer */ /************************************************************************/ +bool first_adc_channel; + void core_callback_t_before_exec(void) {} void core_callback_t_after_exec(void) {} void core_callback_t_new_second(void) {} void core_callback_t_500us(void) {} void core_callback_t_1ms(void) { - /* Read ADC0 */ - ADCA_CH0_MUXCTRL = 10 << 3; // Select pin - ADCA_CH0_CTRL |= ADC_CH_START_bm; // Start conversion - while(!(ADCA_CH0_INTFLAGS & ADC_CH_CHIF_bm)); // Wait for conversion to finish - ADCA_CH0_INTFLAGS = ADC_CH_CHIF_bm; // Clear interrupt bit - if (ADCA_CH0_RES > AdcOffset) - app_regs.REG_ADC_VALUES[0] = (ADCA_CH0_RES & 0x0FFF) - AdcOffset; - else - app_regs.REG_ADC_VALUES[0] = 0; - - /* Read ADC1 */ - ADCA_CH0_MUXCTRL = 9 << 3; // Select pin - ADCA_CH0_CTRL |= ADC_CH_START_bm; // Start conversion - while(!(ADCA_CH0_INTFLAGS & ADC_CH_CHIF_bm)); // Wait for conversion to finish - ADCA_CH0_INTFLAGS = ADC_CH_CHIF_bm; // Clear interrupt bit - if (ADCA_CH0_RES > AdcOffset) - app_regs.REG_ADC_VALUES[1] = (ADCA_CH0_RES & 0x0FFF) - AdcOffset; - else - app_regs.REG_ADC_VALUES[1] = 0; - - //core_func_send_event(ADD_REG_ADC_VALUES, true); + if (app_regs.REG_DATA_STREAM_CONF == GM_DATA_STREAM_1KHz) + { + /* Read ADC */ + core_func_mark_user_timestamp(); + + app_regs.REG_DATA_STREAM[2] = app_regs.REG_SET_ATTENUATION_AND_PLAY_SOUND_OR_FREQ[1]; + app_regs.REG_DATA_STREAM[3] = app_regs.REG_SET_ATTENUATION_AND_PLAY_SOUND_OR_FREQ[2]; + app_regs.REG_DATA_STREAM[4] = app_regs.REG_SET_ATTENUATION_AND_PLAY_SOUND_OR_FREQ[0]; + + /* Start conversation on ADCA Channel 10 */ + first_adc_channel = true; + ADCA_CH0_MUXCTRL = 10 << 3; + ADCA_CH0_CTRL |= ADC_CH_START_bm; + } } /************************************************************************/ diff --git a/Firmware/Firmware.ATXMEGA/SoundCard/app_funcs.c b/Firmware/Firmware.ATXMEGA/SoundCard/app_funcs.c index de27bb2..f310101 100644 --- a/Firmware/Firmware.ATXMEGA/SoundCard/app_funcs.c +++ b/Firmware/Firmware.ATXMEGA/SoundCard/app_funcs.c @@ -12,7 +12,7 @@ extern AppRegs app_regs; void (*app_func_rd_pointer[])(void) = { &app_read_REG_PLAY_SOUND_OR_FREQ, &app_read_REG_STOP, - &app_read_REG_ATTNUATION_LEFT, + &app_read_REG_ATTENUATION_LEFT, &app_read_REG_ATTENUATION_RIGHT, &app_read_REG_ATTENUATION_BOTH, &app_read_REG_SET_ATTENUATION_AND_PLAY_SOUND_OR_FREQ, @@ -21,34 +21,18 @@ void (*app_func_rd_pointer[])(void) = { &app_read_REG_DIGITAL_INPUTS, &app_read_REG_DI0_CONF, &app_read_REG_DI1_CONF, - &app_read_REG_DI2_CONF, &app_read_REG_DI0_SOUND_INDEX, &app_read_REG_DI1_SOUND_INDEX, - &app_read_REG_DI2_SOUND_INDEX, - &app_read_REG_DI0_FREQ, - &app_read_REG_DI1_FREQ, - &app_read_REG_DI2_FREQ, - &app_read_REG_DI0_ATTNUATION_LEFT, - &app_read_REG_DI1_ATTNUATION_LEFT, - &app_read_REG_DI2_ATTNUATION_LEFT, + &app_read_REG_DI0_ATTENUATION_LEFT, + &app_read_REG_DI1_ATTENUATION_LEFT, &app_read_REG_DI0_ATTENUATION_RIGHT, &app_read_REG_DI1_ATTENUATION_RIGHT, - &app_read_REG_DI2_ATTENUATION_RIGHT, - &app_read_REG_DI0_ATTENUATION_AND_SOUND_INDEX, - &app_read_REG_DI1_ATTENUATION_AND_SOUND_INDEX, - &app_read_REG_DI2_ATTENUATION_AND_SOUND_INDEX, - &app_read_REG_DI0_ATTENUATION_AND_FREQUENCY, - &app_read_REG_DI1_ATTENUATION_AND_FREQUENCY, - &app_read_REG_DI2_ATTENUATION_AND_FReQUENCY, &app_read_REG_RESERVED2, &app_read_REG_RESERVED3, &app_read_REG_RESERVED4, &app_read_REG_DO0_CONF, &app_read_REG_DO1_CONF, &app_read_REG_DO2_CONF, - &app_read_REG_DO0_PULSE, - &app_read_REG_DO1_PULSE, - &app_read_REG_DO2_PULSE, &app_read_REG_RESERVED5, &app_read_REG_RESERVED6, &app_read_REG_RESERVED7, @@ -58,19 +42,31 @@ void (*app_func_rd_pointer[])(void) = { &app_read_REG_DO_OUT, &app_read_REG_RESERVED8, &app_read_REG_RESERVED9, - &app_read_REG_ADC_CONF, - &app_read_REG_ADC_VALUES, - &app_read_REG_COMMANDS, + &app_read_REG_DATA_STREAM_CONF, + &app_read_REG_DATA_STREAM, + &app_read_REG_ADC0_CONF, + &app_read_REG_ADC1_CONF, &app_read_REG_RESERVED10, &app_read_REG_RESERVED11, &app_read_REG_RESERVED12, - &app_read_REG_EVNT_ENABLE + &app_read_REG_RESERVED13, + &app_read_REG_RESERVED14, + &app_read_REG_RESERVED15, + &app_read_REG_RESERVED16, + &app_read_REG_RESERVED17, + &app_read_REG_RESERVED18, + &app_read_REG_RESERVED19, + &app_read_REG_RESERVED20, + &app_read_REG_RESERVED21, + &app_read_REG_RESERVED22, + &app_read_REG_RESERVED23, + &app_read_REG_COMMANDS }; bool (*app_func_wr_pointer[])(void*) = { &app_write_REG_PLAY_SOUND_OR_FREQ, &app_write_REG_STOP, - &app_write_REG_ATTNUATION_LEFT, + &app_write_REG_ATTENUATION_LEFT, &app_write_REG_ATTENUATION_RIGHT, &app_write_REG_ATTENUATION_BOTH, &app_write_REG_SET_ATTENUATION_AND_PLAY_SOUND_OR_FREQ, @@ -79,34 +75,18 @@ bool (*app_func_wr_pointer[])(void*) = { &app_write_REG_DIGITAL_INPUTS, &app_write_REG_DI0_CONF, &app_write_REG_DI1_CONF, - &app_write_REG_DI2_CONF, &app_write_REG_DI0_SOUND_INDEX, &app_write_REG_DI1_SOUND_INDEX, - &app_write_REG_DI2_SOUND_INDEX, - &app_write_REG_DI0_FREQ, - &app_write_REG_DI1_FREQ, - &app_write_REG_DI2_FREQ, - &app_write_REG_DI0_ATTNUATION_LEFT, - &app_write_REG_DI1_ATTNUATION_LEFT, - &app_write_REG_DI2_ATTNUATION_LEFT, + &app_write_REG_DI0_ATTENUATION_LEFT, + &app_write_REG_DI1_ATTENUATION_LEFT, &app_write_REG_DI0_ATTENUATION_RIGHT, &app_write_REG_DI1_ATTENUATION_RIGHT, - &app_write_REG_DI2_ATTENUATION_RIGHT, - &app_write_REG_DI0_ATTENUATION_AND_SOUND_INDEX, - &app_write_REG_DI1_ATTENUATION_AND_SOUND_INDEX, - &app_write_REG_DI2_ATTENUATION_AND_SOUND_INDEX, - &app_write_REG_DI0_ATTENUATION_AND_FREQUENCY, - &app_write_REG_DI1_ATTENUATION_AND_FREQUENCY, - &app_write_REG_DI2_ATTENUATION_AND_FReQUENCY, &app_write_REG_RESERVED2, &app_write_REG_RESERVED3, &app_write_REG_RESERVED4, &app_write_REG_DO0_CONF, &app_write_REG_DO1_CONF, &app_write_REG_DO2_CONF, - &app_write_REG_DO0_PULSE, - &app_write_REG_DO1_PULSE, - &app_write_REG_DO2_PULSE, &app_write_REG_RESERVED5, &app_write_REG_RESERVED6, &app_write_REG_RESERVED7, @@ -116,13 +96,25 @@ bool (*app_func_wr_pointer[])(void*) = { &app_write_REG_DO_OUT, &app_write_REG_RESERVED8, &app_write_REG_RESERVED9, - &app_write_REG_ADC_CONF, - &app_write_REG_ADC_VALUES, - &app_write_REG_COMMANDS, + &app_write_REG_DATA_STREAM_CONF, + &app_write_REG_DATA_STREAM, + &app_write_REG_ADC0_CONF, + &app_write_REG_ADC1_CONF, &app_write_REG_RESERVED10, &app_write_REG_RESERVED11, &app_write_REG_RESERVED12, - &app_write_REG_EVNT_ENABLE + &app_write_REG_RESERVED13, + &app_write_REG_RESERVED14, + &app_write_REG_RESERVED15, + &app_write_REG_RESERVED16, + &app_write_REG_RESERVED17, + &app_write_REG_RESERVED18, + &app_write_REG_RESERVED19, + &app_write_REG_RESERVED20, + &app_write_REG_RESERVED21, + &app_write_REG_RESERVED22, + &app_write_REG_RESERVED23, + &app_write_REG_COMMANDS }; @@ -150,7 +142,7 @@ bool app_write_REG_PLAY_SOUND_OR_FREQ(void *a) /* Save the sound being played */ last_sound_triggered = reg; - //par_cmd_start_sound(reg, app_regs.REG_ATTNUATION_LEFT, app_regs.REG_ATTENUATION_RIGHT); + //par_cmd_start_sound(reg, app_regs.REG_ATTENUATION_LEFT, app_regs.REG_ATTENUATION_RIGHT); par_cmd_update_frequency(reg); return true; @@ -177,17 +169,17 @@ bool app_write_REG_STOP(void *a) /************************************************************************/ -/* REG_ATTNUATION_LEFT */ +/* REG_ATTENUATION_LEFT */ /************************************************************************/ -void app_read_REG_ATTNUATION_LEFT(void) {} -bool app_write_REG_ATTNUATION_LEFT(void *a) +void app_read_REG_ATTENUATION_LEFT(void) {} +bool app_write_REG_ATTENUATION_LEFT(void *a) { uint16_t reg = *((uint16_t*)a); app_regs.REG_ATTENUATION_BOTH[0] = reg; app_regs.REG_SET_ATTENUATION_AND_PLAY_SOUND_OR_FREQ[1] = reg; - app_regs.REG_ATTNUATION_LEFT = reg; + app_regs.REG_ATTENUATION_LEFT = reg; par_cmd_update_amplitude_left(reg); @@ -222,7 +214,7 @@ bool app_write_REG_ATTENUATION_BOTH(void *a) { uint16_t *reg = ((uint16_t*)a); - app_regs.REG_ATTNUATION_LEFT = reg[0]; + app_regs.REG_ATTENUATION_LEFT = reg[0]; app_regs.REG_ATTENUATION_RIGHT = reg[1]; app_regs.REG_SET_ATTENUATION_AND_PLAY_SOUND_OR_FREQ[1] = reg[0]; @@ -253,7 +245,7 @@ bool app_write_REG_SET_ATTENUATION_AND_PLAY_SOUND_OR_FREQ(void *a) return false; app_regs.REG_PLAY_SOUND_OR_FREQ = reg[0]; - app_regs.REG_ATTNUATION_LEFT = reg[1]; + app_regs.REG_ATTENUATION_LEFT = reg[1]; app_regs.REG_ATTENUATION_RIGHT = reg[2]; app_regs.REG_ATTENUATION_BOTH[0] = reg[1]; app_regs.REG_ATTENUATION_BOTH[1] = reg[2]; @@ -271,57 +263,21 @@ bool app_write_REG_SET_ATTENUATION_AND_PLAY_SOUND_OR_FREQ(void *a) } -/************************************************************************/ -/* REG_RESERVED0 */ -/************************************************************************/ -void app_read_REG_RESERVED0(void) -{ - //app_regs.REG_RESERVED0 = 0; - -} - -bool app_write_REG_RESERVED0(void *a) -{ - uint8_t reg = *((uint8_t*)a); - - app_regs.REG_RESERVED0 = reg; - return true; -} - - -/************************************************************************/ -/* REG_RESERVED1 */ -/************************************************************************/ -void app_read_REG_RESERVED1(void) -{ - //app_regs.REG_RESERVED1 = 0; - -} - -bool app_write_REG_RESERVED1(void *a) -{ - uint8_t reg = *((uint8_t*)a); - - app_regs.REG_RESERVED1 = reg; - return true; -} - - /************************************************************************/ /* REG_DIGITAL_INPUTS */ /************************************************************************/ void app_read_REG_DIGITAL_INPUTS(void) { - //app_regs.REG_DIGITAL_INPUTS = 0; - + app_regs.REG_DIGITAL_INPUTS = 0; + + app_regs.REG_DIGITAL_INPUTS |= (read_DIN0) ? B_DI0 : 0; + app_regs.REG_DIGITAL_INPUTS |= (read_DIN1) ? B_DI1 : 0; + app_regs.REG_DIGITAL_INPUTS |= (read_DIN2) ? B_DI2 : 0; } bool app_write_REG_DIGITAL_INPUTS(void *a) { - uint8_t reg = *((uint8_t*)a); - - app_regs.REG_DIGITAL_INPUTS = reg; - return true; + return false; } @@ -337,6 +293,8 @@ void app_read_REG_DI0_CONF(void) bool app_write_REG_DI0_CONF(void *a) { uint8_t reg = *((uint8_t*)a); + + if (reg & (~MSK_DI_SEL)) return false; app_regs.REG_DI0_CONF = reg; return true; @@ -355,30 +313,14 @@ void app_read_REG_DI1_CONF(void) bool app_write_REG_DI1_CONF(void *a) { uint8_t reg = *((uint8_t*)a); + + if (reg & (~MSK_DI_SEL)) return false; app_regs.REG_DI1_CONF = reg; return true; } -/************************************************************************/ -/* REG_DI2_CONF */ -/************************************************************************/ -void app_read_REG_DI2_CONF(void) -{ - //app_regs.REG_DI2_CONF = 0; - -} - -bool app_write_REG_DI2_CONF(void *a) -{ - uint8_t reg = *((uint8_t*)a); - - app_regs.REG_DI2_CONF = reg; - return true; -} - - /************************************************************************/ /* REG_DI0_SOUND_INDEX */ /************************************************************************/ @@ -390,7 +332,10 @@ void app_read_REG_DI0_SOUND_INDEX(void) bool app_write_REG_DI0_SOUND_INDEX(void *a) { - uint8_t reg = *((uint8_t*)a); + uint16_t reg = *((uint16_t*)a); + + if (reg <= 1 || reg > 40000) + return false; app_regs.REG_DI0_SOUND_INDEX = reg; return true; @@ -407,136 +352,49 @@ void app_read_REG_DI1_SOUND_INDEX(void) } bool app_write_REG_DI1_SOUND_INDEX(void *a) -{ - uint8_t reg = *((uint8_t*)a); - - app_regs.REG_DI1_SOUND_INDEX = reg; - return true; -} - - -/************************************************************************/ -/* REG_DI2_SOUND_INDEX */ -/************************************************************************/ -void app_read_REG_DI2_SOUND_INDEX(void) -{ - //app_regs.REG_DI2_SOUND_INDEX = 0; - -} - -bool app_write_REG_DI2_SOUND_INDEX(void *a) -{ - uint8_t reg = *((uint8_t*)a); - - app_regs.REG_DI2_SOUND_INDEX = reg; - return true; -} - - -/************************************************************************/ -/* REG_DI0_FREQ */ -/************************************************************************/ -void app_read_REG_DI0_FREQ(void) -{ - //app_regs.REG_DI0_FREQ = 0; - -} - -bool app_write_REG_DI0_FREQ(void *a) -{ - uint16_t reg = *((uint16_t*)a); - - app_regs.REG_DI0_FREQ = reg; - return true; -} - - -/************************************************************************/ -/* REG_DI1_FREQ */ -/************************************************************************/ -void app_read_REG_DI1_FREQ(void) -{ - //app_regs.REG_DI1_FREQ = 0; - -} - -bool app_write_REG_DI1_FREQ(void *a) -{ - uint16_t reg = *((uint16_t*)a); - - app_regs.REG_DI1_FREQ = reg; - return true; -} - - -/************************************************************************/ -/* REG_DI2_FREQ */ -/************************************************************************/ -void app_read_REG_DI2_FREQ(void) -{ - //app_regs.REG_DI2_FREQ = 0; - -} - -bool app_write_REG_DI2_FREQ(void *a) -{ - uint16_t reg = *((uint16_t*)a); - - app_regs.REG_DI2_FREQ = reg; - return true; -} - - -/************************************************************************/ -/* REG_DI0_ATTNUATION_LEFT */ -/************************************************************************/ -void app_read_REG_DI0_ATTNUATION_LEFT(void) -{ - //app_regs.REG_DI0_ATTNUATION_LEFT = 0; - -} - -bool app_write_REG_DI0_ATTNUATION_LEFT(void *a) { uint16_t reg = *((uint16_t*)a); + + if (reg <= 1 || reg > 40000) + return false; - app_regs.REG_DI0_ATTNUATION_LEFT = reg; + app_regs.REG_DI1_SOUND_INDEX = reg; return true; } /************************************************************************/ -/* REG_DI1_ATTNUATION_LEFT */ +/* REG_DI0_ATTENUATION_LEFT */ /************************************************************************/ -void app_read_REG_DI1_ATTNUATION_LEFT(void) +void app_read_REG_DI0_ATTENUATION_LEFT(void) { - //app_regs.REG_DI1_ATTNUATION_LEFT = 0; + //app_regs.REG_DI0_ATTENUATION_LEFT = 0; } -bool app_write_REG_DI1_ATTNUATION_LEFT(void *a) +bool app_write_REG_DI0_ATTENUATION_LEFT(void *a) { uint16_t reg = *((uint16_t*)a); - app_regs.REG_DI1_ATTNUATION_LEFT = reg; + app_regs.REG_DI0_ATTENUATION_LEFT = reg; return true; } /************************************************************************/ -/* REG_DI2_ATTNUATION_LEFT */ +/* REG_DI1_ATTENUATION_LEFT */ /************************************************************************/ -void app_read_REG_DI2_ATTNUATION_LEFT(void) +void app_read_REG_DI1_ATTENUATION_LEFT(void) { - //app_regs.REG_DI2_ATTNUATION_LEFT = 0; + //app_regs.REG_DI1_ATTENUATION_LEFT = 0; } -bool app_write_REG_DI2_ATTNUATION_LEFT(void *a) +bool app_write_REG_DI1_ATTENUATION_LEFT(void *a) { uint16_t reg = *((uint16_t*)a); - app_regs.REG_DI2_ATTNUATION_LEFT = reg; + app_regs.REG_DI1_ATTENUATION_LEFT = reg; return true; } @@ -577,192 +435,6 @@ bool app_write_REG_DI1_ATTENUATION_RIGHT(void *a) } -/************************************************************************/ -/* REG_DI2_ATTENUATION_RIGHT */ -/************************************************************************/ -void app_read_REG_DI2_ATTENUATION_RIGHT(void) -{ - //app_regs.REG_DI2_ATTENUATION_RIGHT = 0; - -} - -bool app_write_REG_DI2_ATTENUATION_RIGHT(void *a) -{ - uint16_t reg = *((uint16_t*)a); - - app_regs.REG_DI2_ATTENUATION_RIGHT = reg; - return true; -} - - -/************************************************************************/ -/* REG_DI0_ATTENUATION_AND_SOUND_INDEX */ -/************************************************************************/ -// This register is an array with 3 positions -void app_read_REG_DI0_ATTENUATION_AND_SOUND_INDEX(void) -{ - //app_regs.REG_DI0_ATTENUATION_AND_SOUND_INDEX[0] = 0; - -} - -bool app_write_REG_DI0_ATTENUATION_AND_SOUND_INDEX(void *a) -{ - uint16_t *reg = ((uint16_t*)a); - - app_regs.REG_DI0_ATTENUATION_AND_SOUND_INDEX[0] = reg[0]; - return true; -} - - -/************************************************************************/ -/* REG_DI1_ATTENUATION_AND_SOUND_INDEX */ -/************************************************************************/ -// This register is an array with 3 positions -void app_read_REG_DI1_ATTENUATION_AND_SOUND_INDEX(void) -{ - //app_regs.REG_DI1_ATTENUATION_AND_SOUND_INDEX[0] = 0; - -} - -bool app_write_REG_DI1_ATTENUATION_AND_SOUND_INDEX(void *a) -{ - uint16_t *reg = ((uint16_t*)a); - - app_regs.REG_DI1_ATTENUATION_AND_SOUND_INDEX[0] = reg[0]; - return true; -} - - -/************************************************************************/ -/* REG_DI2_ATTENUATION_AND_SOUND_INDEX */ -/************************************************************************/ -// This register is an array with 3 positions -void app_read_REG_DI2_ATTENUATION_AND_SOUND_INDEX(void) -{ - //app_regs.REG_DI2_ATTENUATION_AND_SOUND_INDEX[0] = 0; - -} - -bool app_write_REG_DI2_ATTENUATION_AND_SOUND_INDEX(void *a) -{ - uint16_t *reg = ((uint16_t*)a); - - app_regs.REG_DI2_ATTENUATION_AND_SOUND_INDEX[0] = reg[0]; - return true; -} - - -/************************************************************************/ -/* REG_DI0_ATTENUATION_AND_FREQUENCY */ -/************************************************************************/ -// This register is an array with 2 positions -void app_read_REG_DI0_ATTENUATION_AND_FREQUENCY(void) -{ - //app_regs.REG_DI0_ATTENUATION_AND_FREQUENCY[0] = 0; - -} - -bool app_write_REG_DI0_ATTENUATION_AND_FREQUENCY(void *a) -{ - uint16_t *reg = ((uint16_t*)a); - - app_regs.REG_DI0_ATTENUATION_AND_FREQUENCY[0] = reg[0]; - return true; -} - - -/************************************************************************/ -/* REG_DI1_ATTENUATION_AND_FREQUENCY */ -/************************************************************************/ -// This register is an array with 2 positions -void app_read_REG_DI1_ATTENUATION_AND_FREQUENCY(void) -{ - //app_regs.REG_DI1_ATTENUATION_AND_FREQUENCY[0] = 0; - -} - -bool app_write_REG_DI1_ATTENUATION_AND_FREQUENCY(void *a) -{ - uint16_t *reg = ((uint16_t*)a); - - app_regs.REG_DI1_ATTENUATION_AND_FREQUENCY[0] = reg[0]; - return true; -} - - -/************************************************************************/ -/* REG_DI2_ATTENUATION_AND_FReQUENCY */ -/************************************************************************/ -// This register is an array with 2 positions -void app_read_REG_DI2_ATTENUATION_AND_FReQUENCY(void) -{ - //app_regs.REG_DI2_ATTENUATION_AND_FReQUENCY[0] = 0; - -} - -bool app_write_REG_DI2_ATTENUATION_AND_FReQUENCY(void *a) -{ - uint16_t *reg = ((uint16_t*)a); - - app_regs.REG_DI2_ATTENUATION_AND_FReQUENCY[0] = reg[0]; - return true; -} - - -/************************************************************************/ -/* REG_RESERVED2 */ -/************************************************************************/ -void app_read_REG_RESERVED2(void) -{ - //app_regs.REG_RESERVED2 = 0; - -} - -bool app_write_REG_RESERVED2(void *a) -{ - uint8_t reg = *((uint8_t*)a); - - app_regs.REG_RESERVED2 = reg; - return true; -} - - -/************************************************************************/ -/* REG_RESERVED3 */ -/************************************************************************/ -void app_read_REG_RESERVED3(void) -{ - //app_regs.REG_RESERVED3 = 0; - -} - -bool app_write_REG_RESERVED3(void *a) -{ - uint8_t reg = *((uint8_t*)a); - - app_regs.REG_RESERVED3 = reg; - return true; -} - - -/************************************************************************/ -/* REG_RESERVED4 */ -/************************************************************************/ -void app_read_REG_RESERVED4(void) -{ - //app_regs.REG_RESERVED4 = 0; - -} - -bool app_write_REG_RESERVED4(void *a) -{ - uint8_t reg = *((uint8_t*)a); - - app_regs.REG_RESERVED4 = reg; - return true; -} - - /************************************************************************/ /* REG_DO0_CONF */ /************************************************************************/ @@ -775,6 +447,8 @@ void app_read_REG_DO0_CONF(void) bool app_write_REG_DO0_CONF(void *a) { uint8_t reg = *((uint8_t*)a); + + if (reg & (~MSK_DO_SEL)) return false; app_regs.REG_DO0_CONF = reg; return true; @@ -793,6 +467,8 @@ void app_read_REG_DO1_CONF(void) bool app_write_REG_DO1_CONF(void *a) { uint8_t reg = *((uint8_t*)a); + + if (reg & (~MSK_DO_SEL)) return false; app_regs.REG_DO1_CONF = reg; return true; @@ -810,121 +486,15 @@ void app_read_REG_DO2_CONF(void) bool app_write_REG_DO2_CONF(void *a) { - uint8_t reg = *((uint8_t*)a); + uint8_t reg = *((uint8_t*)a); + + if (reg & (~MSK_DO_SEL)) return false; app_regs.REG_DO2_CONF = reg; return true; } -/************************************************************************/ -/* REG_DO0_PULSE */ -/************************************************************************/ -void app_read_REG_DO0_PULSE(void) -{ - //app_regs.REG_DO0_PULSE = 0; - -} - -bool app_write_REG_DO0_PULSE(void *a) -{ - uint8_t reg = *((uint8_t*)a); - - app_regs.REG_DO0_PULSE = reg; - return true; -} - - -/************************************************************************/ -/* REG_DO1_PULSE */ -/************************************************************************/ -void app_read_REG_DO1_PULSE(void) -{ - //app_regs.REG_DO1_PULSE = 0; - -} - -bool app_write_REG_DO1_PULSE(void *a) -{ - uint8_t reg = *((uint8_t*)a); - - app_regs.REG_DO1_PULSE = reg; - return true; -} - - -/************************************************************************/ -/* REG_DO2_PULSE */ -/************************************************************************/ -void app_read_REG_DO2_PULSE(void) -{ - //app_regs.REG_DO2_PULSE = 0; - -} - -bool app_write_REG_DO2_PULSE(void *a) -{ - uint8_t reg = *((uint8_t*)a); - - app_regs.REG_DO2_PULSE = reg; - return true; -} - - -/************************************************************************/ -/* REG_RESERVED5 */ -/************************************************************************/ -void app_read_REG_RESERVED5(void) -{ - //app_regs.REG_RESERVED5 = 0; - -} - -bool app_write_REG_RESERVED5(void *a) -{ - uint8_t reg = *((uint8_t*)a); - - app_regs.REG_RESERVED5 = reg; - return true; -} - - -/************************************************************************/ -/* REG_RESERVED6 */ -/************************************************************************/ -void app_read_REG_RESERVED6(void) -{ - //app_regs.REG_RESERVED6 = 0; - -} - -bool app_write_REG_RESERVED6(void *a) -{ - uint8_t reg = *((uint8_t*)a); - - app_regs.REG_RESERVED6 = reg; - return true; -} - - -/************************************************************************/ -/* REG_RESERVED7 */ -/************************************************************************/ -void app_read_REG_RESERVED7(void) -{ - //app_regs.REG_RESERVED7 = 0; - -} - -bool app_write_REG_RESERVED7(void *a) -{ - uint8_t reg = *((uint8_t*)a); - - app_regs.REG_RESERVED7 = reg; - return true; -} - - /************************************************************************/ /* REG_DO_SET */ /************************************************************************/ @@ -936,9 +506,9 @@ bool app_write_REG_DO_SET(void *a) { uint8_t reg = *((uint8_t*)a); - if (reg & B_DO0) set_DOUT0; - if (reg & B_DO1) set_DOUT1; - if (reg & B_DO2) set_DOUT2; + if (reg & B_DO0) set_DOUT0; + if (reg & B_DO1) set_DOUT1; + if (reg & B_DO2) set_DOUT2; app_regs.REG_DO_SET = reg; return true; @@ -958,7 +528,7 @@ bool app_write_REG_DO_CLEAR(void *a) if (reg & B_DO0) clr_DOUT0; if (reg & B_DO1) clr_DOUT1; - if (reg & B_DO1) clr_DOUT1; + if (reg & B_DO2) clr_DOUT2; app_regs.REG_DO_CLEAR = reg; return true; @@ -978,7 +548,7 @@ bool app_write_REG_DO_TOGGLE(void *a) if (reg & B_DO0) tgl_DOUT0; if (reg & B_DO1) tgl_DOUT1; - if (reg & B_DO1) tgl_DOUT1; + if (reg & B_DO2) tgl_DOUT2; app_regs.REG_DO_TOGGLE = reg; return true; @@ -991,17 +561,17 @@ bool app_write_REG_DO_TOGGLE(void *a) void app_read_REG_DO_OUT(void) { app_regs.REG_DO_OUT = read_DOUT0 ? B_DO0 : 0; - app_regs.REG_DO_OUT |= read_DOUT1 ? B_DO1 : 0; - app_regs.REG_DO_OUT |= read_DOUT2 ? B_DO2 : 0; + app_regs.REG_DO_OUT |= read_DOUT1 ? B_DO1 : 0; + app_regs.REG_DO_OUT |= read_DOUT2 ? B_DO2 : 0; } bool app_write_REG_DO_OUT(void *a) { uint8_t reg = *((uint8_t*)a); - if (reg & B_DO0) set_DOUT0; else clr_DOUT0; - if (reg & B_DO1) set_DOUT1; else clr_DOUT1; - if (reg & B_DO2) set_DOUT2; else clr_DOUT2; + if (reg & B_DO0) set_DOUT0; else clr_DOUT0; + if (reg & B_DO1) set_DOUT1; else clr_DOUT1; + if (reg & B_DO2) set_DOUT2; else clr_DOUT2; app_regs.REG_DO_OUT = reg; return true; @@ -1009,74 +579,86 @@ bool app_write_REG_DO_OUT(void *a) /************************************************************************/ -/* REG_RESERVED8 */ +/* REG_DATA_STREAM_CONF */ /************************************************************************/ -void app_read_REG_RESERVED8(void) +void app_read_REG_DATA_STREAM_CONF(void) { - //app_regs.REG_RESERVED8 = 0; + //app_regs.REG_DATA_STREAM_CONF = 0; } -bool app_write_REG_RESERVED8(void *a) +bool app_write_REG_DATA_STREAM_CONF(void *a) { uint8_t reg = *((uint8_t*)a); + + if (reg & (~MSK_DATA_STREAM_SEL)) + { + return false; + } - app_regs.REG_RESERVED8 = reg; + app_regs.REG_DATA_STREAM_CONF = reg; return true; } /************************************************************************/ -/* REG_RESERVED9 */ +/* REG_DATA_STREAM */ /************************************************************************/ -void app_read_REG_RESERVED9(void) +// This register is an array with 5 positions +void app_read_REG_DATA_STREAM(void) { - //app_regs.REG_RESERVED9 = 0; + //app_regs.REG_DATA_STREAM[0] = 0; } -bool app_write_REG_RESERVED9(void *a) +bool app_write_REG_DATA_STREAM(void *a) { - uint8_t reg = *((uint8_t*)a); - - app_regs.REG_RESERVED9 = reg; - return true; + return false; } /************************************************************************/ -/* REG_ADC_CONF */ +/* REG_ADC0_CONF */ /************************************************************************/ -void app_read_REG_ADC_CONF(void) +void app_read_REG_ADC0_CONF(void) { - //app_regs.REG_ADC_CONF = 0; + //app_regs.REG_ADC0_CONF = 0; } -bool app_write_REG_ADC_CONF(void *a) +bool app_write_REG_ADC0_CONF(void *a) { uint8_t reg = *((uint8_t*)a); + + if (reg & (~MSK_ADC0_SEL)) + { + return false; + } - app_regs.REG_ADC_CONF = reg; + app_regs.REG_ADC0_CONF = reg; return true; } /************************************************************************/ -/* REG_ADC_VALUES */ +/* REG_ADC1_CONF */ /************************************************************************/ -// This register is an array with 5 positions -void app_read_REG_ADC_VALUES(void) +void app_read_REG_ADC1_CONF(void) { - //app_regs.REG_ADC_VALUES[0] = 0; + //app_regs.REG_ADC1_CONF = 0; } -bool app_write_REG_ADC_VALUES(void *a) +bool app_write_REG_ADC1_CONF(void *a) { - uint16_t *reg = ((uint16_t*)a); + uint8_t reg = *((uint8_t*)a); + + if (reg & (~MSK_ADC1_SEL)) + { + return false; + } - app_regs.REG_ADC_VALUES[0] = reg[0]; + app_regs.REG_ADC1_CONF = reg; return true; } @@ -1106,72 +688,54 @@ bool app_write_REG_COMMANDS(void *a) /************************************************************************/ -/* REG_RESERVED10 */ -/************************************************************************/ -void app_read_REG_RESERVED10(void) -{ - //app_regs.REG_RESERVED10 = 0; - -} - -bool app_write_REG_RESERVED10(void *a) -{ - uint8_t reg = *((uint8_t*)a); - - app_regs.REG_RESERVED10 = reg; - return true; -} - - -/************************************************************************/ -/* REG_RESERVED11 */ -/************************************************************************/ -void app_read_REG_RESERVED11(void) -{ - //app_regs.REG_RESERVED11 = 0; - -} - -bool app_write_REG_RESERVED11(void *a) -{ - uint8_t reg = *((uint8_t*)a); - - app_regs.REG_RESERVED11 = reg; - return true; -} - - -/************************************************************************/ -/* REG_RESERVED12 */ -/************************************************************************/ -void app_read_REG_RESERVED12(void) -{ - //app_regs.REG_RESERVED12 = 0; - -} - -bool app_write_REG_RESERVED12(void *a) -{ - uint8_t reg = *((uint8_t*)a); - - app_regs.REG_RESERVED12 = reg; - return true; -} - - -/************************************************************************/ -/* REG_EVNT_ENABLE */ -/************************************************************************/ -void app_read_REG_EVNT_ENABLE(void) -{ - //app_regs.REG_EVNT_ENABLE = 0; - -} - -bool app_write_REG_EVNT_ENABLE(void *a) -{ - uint8_t reg = *((uint8_t*)a); - - app_regs.REG_EVNT_ENABLE = reg; - return true; -} \ No newline at end of file +/* All REG_RESERVEDx */ +/************************************************************************/ +void app_read_REG_RESERVED0 (void) {} +void app_read_REG_RESERVED1 (void) {} +void app_read_REG_RESERVED2 (void) {} +void app_read_REG_RESERVED3 (void) {} +void app_read_REG_RESERVED4 (void) {} +void app_read_REG_RESERVED5 (void) {} +void app_read_REG_RESERVED6 (void) {} +void app_read_REG_RESERVED7 (void) {} +void app_read_REG_RESERVED8 (void) {} +void app_read_REG_RESERVED9 (void) {} +void app_read_REG_RESERVED10 (void) {} +void app_read_REG_RESERVED11 (void) {} +void app_read_REG_RESERVED12 (void) {} +void app_read_REG_RESERVED13 (void) {} +void app_read_REG_RESERVED14 (void) {} +void app_read_REG_RESERVED15 (void) {} +void app_read_REG_RESERVED16 (void) {} +void app_read_REG_RESERVED17 (void) {} +void app_read_REG_RESERVED18 (void) {} +void app_read_REG_RESERVED19 (void) {} +void app_read_REG_RESERVED20 (void) {} +void app_read_REG_RESERVED21 (void) {} +void app_read_REG_RESERVED22 (void) {} +void app_read_REG_RESERVED23 (void) {} + +bool app_write_REG_RESERVED0 (void *a) { app_regs.REG_RESERVED0 = *((uint8_t*)a); return true; } +bool app_write_REG_RESERVED1 (void *a) { app_regs.REG_RESERVED1 = *((uint8_t*)a); return true; } +bool app_write_REG_RESERVED2 (void *a) { app_regs.REG_RESERVED2 = *((uint8_t*)a); return true; } +bool app_write_REG_RESERVED3 (void *a) { app_regs.REG_RESERVED3 = *((uint8_t*)a); return true; } +bool app_write_REG_RESERVED4 (void *a) { app_regs.REG_RESERVED4 = *((uint8_t*)a); return true; } +bool app_write_REG_RESERVED5 (void *a) { app_regs.REG_RESERVED5 = *((uint8_t*)a); return true; } +bool app_write_REG_RESERVED6 (void *a) { app_regs.REG_RESERVED6 = *((uint8_t*)a); return true; } +bool app_write_REG_RESERVED7 (void *a) { app_regs.REG_RESERVED7 = *((uint8_t*)a); return true; } +bool app_write_REG_RESERVED8 (void *a) { app_regs.REG_RESERVED8 = *((uint8_t*)a); return true; } +bool app_write_REG_RESERVED9 (void *a) { app_regs.REG_RESERVED9 = *((uint8_t*)a); return true; } +bool app_write_REG_RESERVED10 (void *a) { app_regs.REG_RESERVED10 = *((uint8_t*)a); return true; } +bool app_write_REG_RESERVED11 (void *a) { app_regs.REG_RESERVED11 = *((uint8_t*)a); return true; } +bool app_write_REG_RESERVED12 (void *a) { app_regs.REG_RESERVED12 = *((uint8_t*)a); return true; } +bool app_write_REG_RESERVED13 (void *a) { app_regs.REG_RESERVED13 = *((uint8_t*)a); return true; } +bool app_write_REG_RESERVED14 (void *a) { app_regs.REG_RESERVED14 = *((uint8_t*)a); return true; } +bool app_write_REG_RESERVED15 (void *a) { app_regs.REG_RESERVED15 = *((uint8_t*)a); return true; } +bool app_write_REG_RESERVED16 (void *a) { app_regs.REG_RESERVED16 = *((uint8_t*)a); return true; } +bool app_write_REG_RESERVED17 (void *a) { app_regs.REG_RESERVED17 = *((uint8_t*)a); return true; } +bool app_write_REG_RESERVED18 (void *a) { app_regs.REG_RESERVED18 = *((uint8_t*)a); return true; } +bool app_write_REG_RESERVED19 (void *a) { app_regs.REG_RESERVED19 = *((uint8_t*)a); return true; } +bool app_write_REG_RESERVED20 (void *a) { app_regs.REG_RESERVED20 = *((uint8_t*)a); return true; } +bool app_write_REG_RESERVED21 (void *a) { app_regs.REG_RESERVED21 = *((uint8_t*)a); return true; } +bool app_write_REG_RESERVED22 (void *a) { app_regs.REG_RESERVED22 = *((uint8_t*)a); return true; } +bool app_write_REG_RESERVED23 (void *a) { app_regs.REG_RESERVED23 = *((uint8_t*)a); return true; } diff --git a/Firmware/Firmware.ATXMEGA/SoundCard/app_funcs.h b/Firmware/Firmware.ATXMEGA/SoundCard/app_funcs.h index 12b2f7d..0026514 100644 --- a/Firmware/Firmware.ATXMEGA/SoundCard/app_funcs.h +++ b/Firmware/Firmware.ATXMEGA/SoundCard/app_funcs.h @@ -22,7 +22,7 @@ /************************************************************************/ void app_read_REG_PLAY_SOUND_OR_FREQ(void); void app_read_REG_STOP(void); -void app_read_REG_ATTNUATION_LEFT(void); +void app_read_REG_ATTENUATION_LEFT(void); void app_read_REG_ATTENUATION_RIGHT(void); void app_read_REG_ATTENUATION_BOTH(void); void app_read_REG_SET_ATTENUATION_AND_PLAY_SOUND_OR_FREQ(void); @@ -31,34 +31,18 @@ void app_read_REG_RESERVED1(void); void app_read_REG_DIGITAL_INPUTS(void); void app_read_REG_DI0_CONF(void); void app_read_REG_DI1_CONF(void); -void app_read_REG_DI2_CONF(void); void app_read_REG_DI0_SOUND_INDEX(void); void app_read_REG_DI1_SOUND_INDEX(void); -void app_read_REG_DI2_SOUND_INDEX(void); -void app_read_REG_DI0_FREQ(void); -void app_read_REG_DI1_FREQ(void); -void app_read_REG_DI2_FREQ(void); -void app_read_REG_DI0_ATTNUATION_LEFT(void); -void app_read_REG_DI1_ATTNUATION_LEFT(void); -void app_read_REG_DI2_ATTNUATION_LEFT(void); +void app_read_REG_DI0_ATTENUATION_LEFT(void); +void app_read_REG_DI1_ATTENUATION_LEFT(void); void app_read_REG_DI0_ATTENUATION_RIGHT(void); void app_read_REG_DI1_ATTENUATION_RIGHT(void); -void app_read_REG_DI2_ATTENUATION_RIGHT(void); -void app_read_REG_DI0_ATTENUATION_AND_SOUND_INDEX(void); -void app_read_REG_DI1_ATTENUATION_AND_SOUND_INDEX(void); -void app_read_REG_DI2_ATTENUATION_AND_SOUND_INDEX(void); -void app_read_REG_DI0_ATTENUATION_AND_FREQUENCY(void); -void app_read_REG_DI1_ATTENUATION_AND_FREQUENCY(void); -void app_read_REG_DI2_ATTENUATION_AND_FReQUENCY(void); void app_read_REG_RESERVED2(void); void app_read_REG_RESERVED3(void); void app_read_REG_RESERVED4(void); void app_read_REG_DO0_CONF(void); void app_read_REG_DO1_CONF(void); void app_read_REG_DO2_CONF(void); -void app_read_REG_DO0_PULSE(void); -void app_read_REG_DO1_PULSE(void); -void app_read_REG_DO2_PULSE(void); void app_read_REG_RESERVED5(void); void app_read_REG_RESERVED6(void); void app_read_REG_RESERVED7(void); @@ -68,17 +52,29 @@ void app_read_REG_DO_TOGGLE(void); void app_read_REG_DO_OUT(void); void app_read_REG_RESERVED8(void); void app_read_REG_RESERVED9(void); -void app_read_REG_ADC_CONF(void); -void app_read_REG_ADC_VALUES(void); -void app_read_REG_COMMANDS(void); +void app_read_REG_DATA_STREAM_CONF(void); +void app_read_REG_DATA_STREAM(void); +void app_read_REG_ADC0_CONF(void); +void app_read_REG_ADC1_CONF(void); void app_read_REG_RESERVED10(void); void app_read_REG_RESERVED11(void); void app_read_REG_RESERVED12(void); -void app_read_REG_EVNT_ENABLE(void); +void app_read_REG_RESERVED13(void); +void app_read_REG_RESERVED14(void); +void app_read_REG_RESERVED15(void); +void app_read_REG_RESERVED16(void); +void app_read_REG_RESERVED17(void); +void app_read_REG_RESERVED18(void); +void app_read_REG_RESERVED19(void); +void app_read_REG_RESERVED20(void); +void app_read_REG_RESERVED21(void); +void app_read_REG_RESERVED22(void); +void app_read_REG_RESERVED23(void); +void app_read_REG_COMMANDS(void); bool app_write_REG_PLAY_SOUND_OR_FREQ(void *a); bool app_write_REG_STOP(void *a); -bool app_write_REG_ATTNUATION_LEFT(void *a); +bool app_write_REG_ATTENUATION_LEFT(void *a); bool app_write_REG_ATTENUATION_RIGHT(void *a); bool app_write_REG_ATTENUATION_BOTH(void *a); bool app_write_REG_SET_ATTENUATION_AND_PLAY_SOUND_OR_FREQ(void *a); @@ -87,34 +83,18 @@ bool app_write_REG_RESERVED1(void *a); bool app_write_REG_DIGITAL_INPUTS(void *a); bool app_write_REG_DI0_CONF(void *a); bool app_write_REG_DI1_CONF(void *a); -bool app_write_REG_DI2_CONF(void *a); bool app_write_REG_DI0_SOUND_INDEX(void *a); bool app_write_REG_DI1_SOUND_INDEX(void *a); -bool app_write_REG_DI2_SOUND_INDEX(void *a); -bool app_write_REG_DI0_FREQ(void *a); -bool app_write_REG_DI1_FREQ(void *a); -bool app_write_REG_DI2_FREQ(void *a); -bool app_write_REG_DI0_ATTNUATION_LEFT(void *a); -bool app_write_REG_DI1_ATTNUATION_LEFT(void *a); -bool app_write_REG_DI2_ATTNUATION_LEFT(void *a); +bool app_write_REG_DI0_ATTENUATION_LEFT(void *a); +bool app_write_REG_DI1_ATTENUATION_LEFT(void *a); bool app_write_REG_DI0_ATTENUATION_RIGHT(void *a); bool app_write_REG_DI1_ATTENUATION_RIGHT(void *a); -bool app_write_REG_DI2_ATTENUATION_RIGHT(void *a); -bool app_write_REG_DI0_ATTENUATION_AND_SOUND_INDEX(void *a); -bool app_write_REG_DI1_ATTENUATION_AND_SOUND_INDEX(void *a); -bool app_write_REG_DI2_ATTENUATION_AND_SOUND_INDEX(void *a); -bool app_write_REG_DI0_ATTENUATION_AND_FREQUENCY(void *a); -bool app_write_REG_DI1_ATTENUATION_AND_FREQUENCY(void *a); -bool app_write_REG_DI2_ATTENUATION_AND_FReQUENCY(void *a); bool app_write_REG_RESERVED2(void *a); bool app_write_REG_RESERVED3(void *a); bool app_write_REG_RESERVED4(void *a); bool app_write_REG_DO0_CONF(void *a); bool app_write_REG_DO1_CONF(void *a); bool app_write_REG_DO2_CONF(void *a); -bool app_write_REG_DO0_PULSE(void *a); -bool app_write_REG_DO1_PULSE(void *a); -bool app_write_REG_DO2_PULSE(void *a); bool app_write_REG_RESERVED5(void *a); bool app_write_REG_RESERVED6(void *a); bool app_write_REG_RESERVED7(void *a); @@ -124,13 +104,25 @@ bool app_write_REG_DO_TOGGLE(void *a); bool app_write_REG_DO_OUT(void *a); bool app_write_REG_RESERVED8(void *a); bool app_write_REG_RESERVED9(void *a); -bool app_write_REG_ADC_CONF(void *a); -bool app_write_REG_ADC_VALUES(void *a); -bool app_write_REG_COMMANDS(void *a); +bool app_write_REG_DATA_STREAM_CONF(void *a); +bool app_write_REG_DATA_STREAM(void *a); +bool app_write_REG_ADC0_CONF(void *a); +bool app_write_REG_ADC1_CONF(void *a); bool app_write_REG_RESERVED10(void *a); bool app_write_REG_RESERVED11(void *a); bool app_write_REG_RESERVED12(void *a); -bool app_write_REG_EVNT_ENABLE(void *a); +bool app_write_REG_RESERVED13(void *a); +bool app_write_REG_RESERVED14(void *a); +bool app_write_REG_RESERVED15(void *a); +bool app_write_REG_RESERVED16(void *a); +bool app_write_REG_RESERVED17(void *a); +bool app_write_REG_RESERVED18(void *a); +bool app_write_REG_RESERVED19(void *a); +bool app_write_REG_RESERVED20(void *a); +bool app_write_REG_RESERVED21(void *a); +bool app_write_REG_RESERVED22(void *a); +bool app_write_REG_RESERVED23(void *a); +bool app_write_REG_COMMANDS(void *a); #endif /* _APP_FUNCTIONS_H_ */ \ No newline at end of file diff --git a/Firmware/Firmware.ATXMEGA/SoundCard/app_ios_and_regs.c b/Firmware/Firmware.ATXMEGA/SoundCard/app_ios_and_regs.c index 59375bd..58a5359 100644 --- a/Firmware/Firmware.ATXMEGA/SoundCard/app_ios_and_regs.c +++ b/Firmware/Firmware.ATXMEGA/SoundCard/app_ios_and_regs.c @@ -7,9 +7,9 @@ /************************************************************************/ void init_ios(void) { /* Configure input pins */ - io_pin2in(&PORTB, 0, PULL_IO_UP, SENSE_IO_EDGE_RISING); // DIN0 + io_pin2in(&PORTB, 0, PULL_IO_UP, SENSE_IO_EDGES_BOTH); // DIN0 io_pin2in(&PORTD, 0, PULL_IO_UP, SENSE_IO_EDGES_BOTH); // DIN1 - io_pin2in(&PORTC, 0, PULL_IO_UP, SENSE_IO_EDGES_BOTH); // DIN2 + io_pin2in(&PORTC, 0, PULL_IO_UP, SENSE_IO_NO_INT_USED); // DIN2 io_pin2in(&PORTC, 5, PULL_IO_UP, SENSE_IO_EDGE_RISING); // CMD_LATCHED io_pin2in(&PORTD, 5, PULL_IO_UP, SENSE_IO_EDGE_RISING); // CMD_NOT_EXEC io_pin2in(&PORTC, 6, PULL_IO_UP, SENSE_IO_EDGES_BOTH); // SOUND_IS_ON @@ -17,7 +17,6 @@ void init_ios(void) /* Configure input interrupts */ io_set_int(&PORTB, INT_LEVEL_LOW, 0, (1<<0), false); // DIN0 io_set_int(&PORTD, INT_LEVEL_LOW, 0, (1<<0), false); // DIN1 - //io_set_int(&PORTC, INT_LEVEL_LOW, 0, (1<<0), false); // DIN2 io_set_int(&PORTC, INT_LEVEL_LOW, 1, (1<<5), false); // CMD_LATCHED io_set_int(&PORTC, INT_LEVEL_LOW, 0, (1<<6), false); // SOUND_IS_ON @@ -69,19 +68,6 @@ uint8_t app_regs_type[] = { TYPE_U8, TYPE_U8, TYPE_U8, - TYPE_U8, - TYPE_U8, - TYPE_U8, - TYPE_U8, - TYPE_U16, - TYPE_U16, - TYPE_U16, - TYPE_U16, - TYPE_U16, - TYPE_U16, - TYPE_U16, - TYPE_U16, - TYPE_U16, TYPE_U16, TYPE_U16, TYPE_U16, @@ -104,10 +90,19 @@ uint8_t app_regs_type[] = { TYPE_U8, TYPE_U8, TYPE_U8, + TYPE_U16, + TYPE_U8, + TYPE_U8, + TYPE_U8, + TYPE_U8, + TYPE_U8, + TYPE_U8, + TYPE_U8, + TYPE_U8, + TYPE_U8, TYPE_U8, TYPE_U8, TYPE_U8, - TYPE_U16, TYPE_U8, TYPE_U8, TYPE_U8, @@ -140,12 +135,6 @@ uint16_t app_regs_n_elements[] = { 1, 1, 1, - 3, - 3, - 3, - 2, - 2, - 2, 1, 1, 1, @@ -155,6 +144,9 @@ uint16_t app_regs_n_elements[] = { 1, 1, 1, + 5, + 1, + 1, 1, 1, 1, @@ -165,7 +157,6 @@ uint16_t app_regs_n_elements[] = { 1, 1, 1, - 5, 1, 1, 1, @@ -176,7 +167,7 @@ uint16_t app_regs_n_elements[] = { uint8_t *app_regs_pointer[] = { (uint8_t*)(&app_regs.REG_PLAY_SOUND_OR_FREQ), (uint8_t*)(&app_regs.REG_STOP), - (uint8_t*)(&app_regs.REG_ATTNUATION_LEFT), + (uint8_t*)(&app_regs.REG_ATTENUATION_LEFT), (uint8_t*)(&app_regs.REG_ATTENUATION_RIGHT), (uint8_t*)(app_regs.REG_ATTENUATION_BOTH), (uint8_t*)(app_regs.REG_SET_ATTENUATION_AND_PLAY_SOUND_OR_FREQ), @@ -185,34 +176,18 @@ uint8_t *app_regs_pointer[] = { (uint8_t*)(&app_regs.REG_DIGITAL_INPUTS), (uint8_t*)(&app_regs.REG_DI0_CONF), (uint8_t*)(&app_regs.REG_DI1_CONF), - (uint8_t*)(&app_regs.REG_DI2_CONF), (uint8_t*)(&app_regs.REG_DI0_SOUND_INDEX), (uint8_t*)(&app_regs.REG_DI1_SOUND_INDEX), - (uint8_t*)(&app_regs.REG_DI2_SOUND_INDEX), - (uint8_t*)(&app_regs.REG_DI0_FREQ), - (uint8_t*)(&app_regs.REG_DI1_FREQ), - (uint8_t*)(&app_regs.REG_DI2_FREQ), - (uint8_t*)(&app_regs.REG_DI0_ATTNUATION_LEFT), - (uint8_t*)(&app_regs.REG_DI1_ATTNUATION_LEFT), - (uint8_t*)(&app_regs.REG_DI2_ATTNUATION_LEFT), + (uint8_t*)(&app_regs.REG_DI0_ATTENUATION_LEFT), + (uint8_t*)(&app_regs.REG_DI1_ATTENUATION_LEFT), (uint8_t*)(&app_regs.REG_DI0_ATTENUATION_RIGHT), (uint8_t*)(&app_regs.REG_DI1_ATTENUATION_RIGHT), - (uint8_t*)(&app_regs.REG_DI2_ATTENUATION_RIGHT), - (uint8_t*)(app_regs.REG_DI0_ATTENUATION_AND_SOUND_INDEX), - (uint8_t*)(app_regs.REG_DI1_ATTENUATION_AND_SOUND_INDEX), - (uint8_t*)(app_regs.REG_DI2_ATTENUATION_AND_SOUND_INDEX), - (uint8_t*)(app_regs.REG_DI0_ATTENUATION_AND_FREQUENCY), - (uint8_t*)(app_regs.REG_DI1_ATTENUATION_AND_FREQUENCY), - (uint8_t*)(app_regs.REG_DI2_ATTENUATION_AND_FReQUENCY), (uint8_t*)(&app_regs.REG_RESERVED2), (uint8_t*)(&app_regs.REG_RESERVED3), (uint8_t*)(&app_regs.REG_RESERVED4), (uint8_t*)(&app_regs.REG_DO0_CONF), (uint8_t*)(&app_regs.REG_DO1_CONF), (uint8_t*)(&app_regs.REG_DO2_CONF), - (uint8_t*)(&app_regs.REG_DO0_PULSE), - (uint8_t*)(&app_regs.REG_DO1_PULSE), - (uint8_t*)(&app_regs.REG_DO2_PULSE), (uint8_t*)(&app_regs.REG_RESERVED5), (uint8_t*)(&app_regs.REG_RESERVED6), (uint8_t*)(&app_regs.REG_RESERVED7), @@ -222,11 +197,23 @@ uint8_t *app_regs_pointer[] = { (uint8_t*)(&app_regs.REG_DO_OUT), (uint8_t*)(&app_regs.REG_RESERVED8), (uint8_t*)(&app_regs.REG_RESERVED9), - (uint8_t*)(&app_regs.REG_ADC_CONF), - (uint8_t*)(app_regs.REG_ADC_VALUES), - (uint8_t*)(&app_regs.REG_COMMANDS), + (uint8_t*)(&app_regs.REG_DATA_STREAM_CONF), + (uint8_t*)(app_regs.REG_DATA_STREAM), + (uint8_t*)(&app_regs.REG_ADC0_CONF), + (uint8_t*)(&app_regs.REG_ADC1_CONF), (uint8_t*)(&app_regs.REG_RESERVED10), (uint8_t*)(&app_regs.REG_RESERVED11), (uint8_t*)(&app_regs.REG_RESERVED12), - (uint8_t*)(&app_regs.REG_EVNT_ENABLE) + (uint8_t*)(&app_regs.REG_RESERVED13), + (uint8_t*)(&app_regs.REG_RESERVED14), + (uint8_t*)(&app_regs.REG_RESERVED15), + (uint8_t*)(&app_regs.REG_RESERVED16), + (uint8_t*)(&app_regs.REG_RESERVED17), + (uint8_t*)(&app_regs.REG_RESERVED18), + (uint8_t*)(&app_regs.REG_RESERVED19), + (uint8_t*)(&app_regs.REG_RESERVED20), + (uint8_t*)(&app_regs.REG_RESERVED21), + (uint8_t*)(&app_regs.REG_RESERVED22), + (uint8_t*)(&app_regs.REG_RESERVED23), + (uint8_t*)(&app_regs.REG_COMMANDS) }; \ No newline at end of file diff --git a/Firmware/Firmware.ATXMEGA/SoundCard/app_ios_and_regs.h b/Firmware/Firmware.ATXMEGA/SoundCard/app_ios_and_regs.h index 3f61327..e9cc3b6 100644 --- a/Firmware/Firmware.ATXMEGA/SoundCard/app_ios_and_regs.h +++ b/Firmware/Firmware.ATXMEGA/SoundCard/app_ios_and_regs.h @@ -123,7 +123,7 @@ typedef struct { uint16_t REG_PLAY_SOUND_OR_FREQ; uint8_t REG_STOP; - uint16_t REG_ATTNUATION_LEFT; + uint16_t REG_ATTENUATION_LEFT; uint16_t REG_ATTENUATION_RIGHT; uint16_t REG_ATTENUATION_BOTH[2]; uint16_t REG_SET_ATTENUATION_AND_PLAY_SOUND_OR_FREQ[3]; @@ -132,34 +132,18 @@ typedef struct uint8_t REG_DIGITAL_INPUTS; uint8_t REG_DI0_CONF; uint8_t REG_DI1_CONF; - uint8_t REG_DI2_CONF; - uint8_t REG_DI0_SOUND_INDEX; - uint8_t REG_DI1_SOUND_INDEX; - uint8_t REG_DI2_SOUND_INDEX; - uint16_t REG_DI0_FREQ; - uint16_t REG_DI1_FREQ; - uint16_t REG_DI2_FREQ; - uint16_t REG_DI0_ATTNUATION_LEFT; - uint16_t REG_DI1_ATTNUATION_LEFT; - uint16_t REG_DI2_ATTNUATION_LEFT; + uint16_t REG_DI0_SOUND_INDEX; + uint16_t REG_DI1_SOUND_INDEX; + uint16_t REG_DI0_ATTENUATION_LEFT; + uint16_t REG_DI1_ATTENUATION_LEFT; uint16_t REG_DI0_ATTENUATION_RIGHT; uint16_t REG_DI1_ATTENUATION_RIGHT; - uint16_t REG_DI2_ATTENUATION_RIGHT; - uint16_t REG_DI0_ATTENUATION_AND_SOUND_INDEX[3]; - uint16_t REG_DI1_ATTENUATION_AND_SOUND_INDEX[3]; - uint16_t REG_DI2_ATTENUATION_AND_SOUND_INDEX[3]; - uint16_t REG_DI0_ATTENUATION_AND_FREQUENCY[2]; - uint16_t REG_DI1_ATTENUATION_AND_FREQUENCY[2]; - uint16_t REG_DI2_ATTENUATION_AND_FReQUENCY[2]; uint8_t REG_RESERVED2; uint8_t REG_RESERVED3; uint8_t REG_RESERVED4; uint8_t REG_DO0_CONF; uint8_t REG_DO1_CONF; uint8_t REG_DO2_CONF; - uint8_t REG_DO0_PULSE; - uint8_t REG_DO1_PULSE; - uint8_t REG_DO2_PULSE; uint8_t REG_RESERVED5; uint8_t REG_RESERVED6; uint8_t REG_RESERVED7; @@ -169,13 +153,25 @@ typedef struct uint8_t REG_DO_OUT; uint8_t REG_RESERVED8; uint8_t REG_RESERVED9; - uint8_t REG_ADC_CONF; - uint16_t REG_ADC_VALUES[5]; - uint8_t REG_COMMANDS; + uint8_t REG_DATA_STREAM_CONF; + uint16_t REG_DATA_STREAM[5]; + uint8_t REG_ADC0_CONF; + uint8_t REG_ADC1_CONF; uint8_t REG_RESERVED10; uint8_t REG_RESERVED11; uint8_t REG_RESERVED12; - uint8_t REG_EVNT_ENABLE; + uint8_t REG_RESERVED13; + uint8_t REG_RESERVED14; + uint8_t REG_RESERVED15; + uint8_t REG_RESERVED16; + uint8_t REG_RESERVED17; + uint8_t REG_RESERVED18; + uint8_t REG_RESERVED19; + uint8_t REG_RESERVED20; + uint8_t REG_RESERVED21; + uint8_t REG_RESERVED22; + uint8_t REG_RESERVED23; + uint8_t REG_COMMANDS; } AppRegs; /************************************************************************/ @@ -184,7 +180,7 @@ typedef struct /* Registers */ #define ADD_REG_PLAY_SOUND_OR_FREQ 32 // U16 Starts the sound index (if < 32) or frequency (if >= 32) #define ADD_REG_STOP 33 // U8 Any value will stops the current sound -#define ADD_REG_ATTNUATION_LEFT 34 // U16 Configure left channel's attenuation (1 LSB is 0.1dB) +#define ADD_REG_ATTENUATION_LEFT 34 // U16 Configure left channel's attenuation (1 LSB is 0.1dB) #define ADD_REG_ATTENUATION_RIGHT 35 // U16 Configure right channel's attenuation (1 LSB is 0.1dB) #define ADD_REG_ATTENUATION_BOTH 36 // U16 Configures both attenuation on right and left channels [Att R] [Att L] #define ADD_REG_SET_ATTENUATION_AND_PLAY_SOUND_OR_FREQ 37 // U16 Configures attenuation and plays sound index [Att R] [Att L] [Index] @@ -193,50 +189,46 @@ typedef struct #define ADD_REG_DIGITAL_INPUTS 40 // U8 State of the digital inputs #define ADD_REG_DI0_CONF 41 // U8 Configuration of the digital input 0 (DI0) #define ADD_REG_DI1_CONF 42 // U8 Configuration of the digital input 1 (DI1) -#define ADD_REG_DI2_CONF 43 // U8 Configuration of the digital input 2 (DI2) -#define ADD_REG_DI0_SOUND_INDEX 44 // U8 Sound index to be played when triggering DI0 -#define ADD_REG_DI1_SOUND_INDEX 45 // U8 Sound index to be played when triggering DI1 -#define ADD_REG_DI2_SOUND_INDEX 46 // U8 Sound index to be played when triggering DI2 -#define ADD_REG_DI0_FREQ 47 // U16 Sound frequency to be played when triggering DI0 -#define ADD_REG_DI1_FREQ 48 // U16 Sound frequency to be played when triggering DI1 -#define ADD_REG_DI2_FREQ 49 // U16 Sound frequency to be played when triggering DI2 -#define ADD_REG_DI0_ATTNUATION_LEFT 50 // U16 Left channel's attenuation (1 LSB is 0.5dB) when triggering DI0 -#define ADD_REG_DI1_ATTNUATION_LEFT 51 // U16 Left channel's attenuation (1 LSB is 0.5dB) when triggering DI1 -#define ADD_REG_DI2_ATTNUATION_LEFT 52 // U16 Left channel's attenuation (1 LSB is 0.5dB) when triggering DI2 -#define ADD_REG_DI0_ATTENUATION_RIGHT 53 // U16 Right channel's attenuation (1 LSB is 0.5dB) when triggering DI0 -#define ADD_REG_DI1_ATTENUATION_RIGHT 54 // U16 Right channel's attenuation (1 LSB is 0.5dB) when triggering DI1 -#define ADD_REG_DI2_ATTENUATION_RIGHT 55 // U16 Right channel's attenuation (1 LSB is 0.5dB) when triggering DI2 -#define ADD_REG_DI0_ATTENUATION_AND_SOUND_INDEX 56 // U16 Sound index and attenuation to be played when triggering DI0 [Att R] [Att L] [Index] -#define ADD_REG_DI1_ATTENUATION_AND_SOUND_INDEX 57 // U16 Sound index and attenuation to be played when triggering DI1 [Att R] [Att L] [Index] -#define ADD_REG_DI2_ATTENUATION_AND_SOUND_INDEX 58 // U16 Sound index and attenuation to be played when triggering DI2 [Att R] [Att L] [Index] -#define ADD_REG_DI0_ATTENUATION_AND_FREQUENCY 59 // U16 Sound index and attenuation to be played when triggering DI0 [Att BOTH] [Frequency] -#define ADD_REG_DI1_ATTENUATION_AND_FREQUENCY 60 // U16 Sound index and attenuation to be played when triggering DI0 [Att BOTH] [Frequency] -#define ADD_REG_DI2_ATTENUATION_AND_FReQUENCY 61 // U16 Sound index and attenuation to be played when triggering DI0 [Att BOTH] [Frequency] -#define ADD_REG_RESERVED2 62 // U8 Reserved for future purposes -#define ADD_REG_RESERVED3 63 // U8 Reserved for future purposes -#define ADD_REG_RESERVED4 64 // U8 Reserved for future purposes -#define ADD_REG_DO0_CONF 65 // U8 Configuration of the digital output 0 (DO0) -#define ADD_REG_DO1_CONF 66 // U8 Configuration of the digital output 1 (DO1) -#define ADD_REG_DO2_CONF 67 // U8 Configuration of the digital output 1 (DO1) -#define ADD_REG_DO0_PULSE 68 // U8 Pulse for the digital output 0 (DO0) [1:255] -#define ADD_REG_DO1_PULSE 69 // U8 Pulse for the digital output 1 (DO1) [1:255] -#define ADD_REG_DO2_PULSE 70 // U8 Pulse for the digital output 2 (DO2) [1:255] -#define ADD_REG_RESERVED5 71 // U8 Reserved for future purposes -#define ADD_REG_RESERVED6 72 // U8 Reserved for future purposes -#define ADD_REG_RESERVED7 73 // U8 Reserved for future purposes -#define ADD_REG_DO_SET 74 // U8 Set the digital outputs -#define ADD_REG_DO_CLEAR 75 // U8 Clear the digital outputs -#define ADD_REG_DO_TOGGLE 76 // U8 Toggle the digital outputs -#define ADD_REG_DO_OUT 77 // U8 Writes to the digital output -#define ADD_REG_RESERVED8 78 // U8 Reserved for future purposes -#define ADD_REG_RESERVED9 79 // U8 Reserved for future purposes -#define ADD_REG_ADC_CONF 80 // U8 Configuration of Analog Inputs -#define ADD_REG_ADC_VALUES 81 // U16 [ADC0] [ADC1] [ATT LEFT] [ATT RIGHT] [FREQUENCY] Values are 0 if not used +#define ADD_REG_DI0_SOUND_INDEX 43 // U16 Sound index to be played when triggering DI0 +#define ADD_REG_DI1_SOUND_INDEX 44 // U16 Sound index to be played when triggering DI1 +#define ADD_REG_DI0_ATTENUATION_LEFT 45 // U16 Left channel's attenuation (1 LSB is 0.1dB) when triggering DI0 +#define ADD_REG_DI1_ATTENUATION_LEFT 46 // U16 Left channel's attenuation (1 LSB is 0.1dB) when triggering DI1 +#define ADD_REG_DI0_ATTENUATION_RIGHT 47 // U16 Right channel's attenuation (1 LSB is 0.1dB) when triggering DI0 +#define ADD_REG_DI1_ATTENUATION_RIGHT 48 // U16 Right channel's attenuation (1 LSB is 0.1dB) when triggering DI1 +#define ADD_REG_RESERVED2 49 // U8 Reserved for future purposes +#define ADD_REG_RESERVED3 50 // U8 Reserved for future purposes +#define ADD_REG_RESERVED4 51 // U8 Reserved for future purposes +#define ADD_REG_DO0_CONF 52 // U8 Configuration of the digital output 0 (DO0) +#define ADD_REG_DO1_CONF 53 // U8 Configuration of the digital output 1 (DO1) +#define ADD_REG_DO2_CONF 54 // U8 Configuration of the digital output 1 (DO1) +#define ADD_REG_RESERVED5 55 // U8 Reserved for future purposes +#define ADD_REG_RESERVED6 56 // U8 Reserved for future purposes +#define ADD_REG_RESERVED7 57 // U8 Reserved for future purposes +#define ADD_REG_DO_SET 58 // U8 Set the digital outputs +#define ADD_REG_DO_CLEAR 59 // U8 Clear the digital outputs +#define ADD_REG_DO_TOGGLE 60 // U8 Toggle the digital outputs +#define ADD_REG_DO_OUT 61 // U8 Writes to the digital output +#define ADD_REG_RESERVED8 62 // U8 Reserved for future purposes +#define ADD_REG_RESERVED9 63 // U8 Reserved for future purposes +#define ADD_REG_DATA_STREAM_CONF 64 // U8 Configuration of data stream +#define ADD_REG_DATA_STREAM 65 // U16 [ADC0] [ADC1] [ATT LEFT] [ATT RIGHT] [FREQUENCY] Values are 0 if not used +#define ADD_REG_ADC0_CONF 66 // U8 +#define ADD_REG_ADC1_CONF 67 // U8 +#define ADD_REG_RESERVED10 68 // U8 Reserved for future purposes +#define ADD_REG_RESERVED11 69 // U8 Reserved for future purposes +#define ADD_REG_RESERVED12 70 // U8 Reserved for future purposes +#define ADD_REG_RESERVED13 71 // U8 Reserved for future purposes +#define ADD_REG_RESERVED14 72 // U8 Reserved for future purposes +#define ADD_REG_RESERVED15 73 // U8 Reserved for future purposes +#define ADD_REG_RESERVED16 74 // U8 Reserved for future purposes +#define ADD_REG_RESERVED17 75 // U8 Reserved for future purposes +#define ADD_REG_RESERVED18 76 // U8 Reserved for future purposes +#define ADD_REG_RESERVED19 77 // U8 Reserved for future purposes +#define ADD_REG_RESERVED20 78 // U8 Reserved for future purposes +#define ADD_REG_RESERVED21 79 // U8 Reserved for future purposes +#define ADD_REG_RESERVED22 80 // U8 Reserved for future purposes +#define ADD_REG_RESERVED23 81 // U8 Reserved for future purposes #define ADD_REG_COMMANDS 82 // U8 Send commands to PIC32 ucontroller -#define ADD_REG_RESERVED10 83 // U8 Reserved for future purposes -#define ADD_REG_RESERVED11 84 // U8 Reserved for future purposes -#define ADD_REG_RESERVED12 85 // U8 Reserved for future purposes -#define ADD_REG_EVNT_ENABLE 86 // U8 Enable the Events /************************************************************************/ /* PWM Generator registers' memory limits */ @@ -246,47 +238,40 @@ typedef struct /************************************************************************/ /* Memory limits */ #define APP_REGS_ADD_MIN 0x20 -#define APP_REGS_ADD_MAX 0x56 -#define APP_NBYTES_OF_REG_BANK 108 +#define APP_REGS_ADD_MAX 0x52 +#define APP_NBYTES_OF_REG_BANK 77 /************************************************************************/ /* Registers' bits */ /************************************************************************/ #define B_DI0 (1<<0) // Digital input 0 +#define B_DI1 (1<<1) // Digital input 1 +#define B_DI2 (1<<2) // Digital input 2 #define MSK_DI_SEL (7<<0) // #define GM_DI_SYNC (0<<0) // Used as a pure digital input #define GM_DI_START_AND_STOP_SOUND (1<<0) // Starts sound when rising edge and stop when falling edge #define GM_DI_START_SOUND (2<<0) // Starts sound when rising edge #define GM_DI_STOP (3<<0) // Stops sound or frequency when rising edge -#define GM_DI_START_AND_STOP_FREQ (4<<0) // Starts frequency when rising edge and stop when falling edge -#define GM_DI_START_FREQ (5<<0) // Starts frequency when rising edge -#define MSK_DO_SEL (15<<0) // +#define MSK_DO_SEL (1<<0) // #define GM_DO_DIG (0<<0) // Used as a pure digital output -#define GM_DO_DIG_AND_PULSE (1<<0) // The digital output will be high during a period specified by register DOx_PULSE -#define GM_DO_HIGH_WHEN_SOUND (2<<0) // High when the sound is being played -#define GM_DO_PULSE_1MS_WHEN_START (3<<0) // High when sound starts during 1 ms -#define GM_DO_PULSE_10MS_WHEN_START (4<<0) // High when sound starts during 1 0ms -#define GM_DO_PULSE_100MS_WHEN_START (5<<0) // High when sound starts during 100 ms -#define GM_DO_PULSE_1MS_WHEN_STOP (6<<0) // High when sound stops during 1 ms -#define GM_DO_PULSE_10MS_WHEN_STOP (7<<0) // High when sound stops during 10 ms -#define GM_DO_PULSE_100MS_WHEN_STOP (8<<0) // High when sound stops during 100 ms +#define GM_DO_PULSE (1<<0) // Positive pulse when sound starts or frequency changes #define B_DO0 (1<<0) // Digital output 0 #define B_DO1 (1<<1) // Digital output 1 #define B_DO2 (1<<2) // Digital output 2 -#define MSK_ADC_SEL (7<<0) // -#define GM_ADC_NOT (0<<0) // Not used -#define GM_ADC_1KHZ_1KHZ (1<<0) // Use both as a pure analog inputs acquired at 1000 Hz -#define GM_ADC_ABOTH_1KHZ (2<<0) // ADC0 controls amplitude of both channels and ADC1 is an analog input -#define GM_ADC_ALEFT_1KHZ (3<<0) // ADC0 controls left amplitude and ADC1 is an analog input -#define GM_ADC_ARIGHT_1KHZ (4<<0) // ADC0 controls right amplitude and ADC1 is an analog input -#define GM_ADC_ALEFT_ARIGHT (5<<0) // ADC0 controls left amplitude and ADC1 controls right amplitude -#define GM_ADC_ABOTH_FREQ (6<<0) // ADC0 controls both amplitude and ADC1 controls the output frequency +#define MSK_DATA_STREAM_SEL (1<<0) // +#define GM_DATA_STREAM_OFF (0<<0) // Not used +#define GM_DATA_STREAM_1KHz (1<<0) // Use both as a pure analog inputs acquired at 1000 Hz +#define MSK_ADC0_SEL (3<<0) // +#define GM_ADC0_PURE_ANALOG_INPUT (0<<0) // +#define GM_ADC0_CONTROL_LEFT_AMPLITUDE (1<<0) // +#define GM_ADC0_CONTROL_BOTH_AMPLITUDE (2<<0) // +#define MSK_ADC1_SEL (3<<0) // ADC0 controls amplitude of both channels and ADC1 is an analog input +#define GM_ADC1_PURE_ANALOG_INPUT (0<<0) // ADC0 controls left amplitude and ADC1 is an analog input +#define GM_ADC1_CONTROL_RIGHT_AMPLITUDE (1<<0) // ADC0 controls right amplitude and ADC1 is an analog input +#define GM_ADC1_CONTROL_BOTH_AMPLITUDE (2<<0) // ADC0 controls left amplitude and ADC1 controls right amplitude +#define GM_ADC1_CONTROL_FREQUENCY (3<<0) // ADC0 controls both amplitude and ADC1 controls the output frequency #define GM_DIS_BOOTLOADER 0 // Disables bootloader buffers #define GM_EN_BOOTLOADER 1 // Enables bootloader buffers #define GM_DEL_ALL_SOUNDS 255 // Delete all sounds in the sound card -#define B_EVT_PLAY_SOUND_OR_FREQ (1<<0) // Event of register PLAY_SOUND_OR_FREQ -#define B_EVT_STOP (1<<1) // Event of register STOP -#define B_EVT_DIGITAL_INPUTS (1<<2) // Event of register DIGITAL_INPUTS -#define B_EVT_ADC_VALUES (1<<3) // Event of register ATTENUATION_BOTH #endif /* _APP_REGS_H_ */ \ No newline at end of file diff --git a/Firmware/Firmware.ATXMEGA/SoundCard/interrupts.c b/Firmware/Firmware.ATXMEGA/SoundCard/interrupts.c index ae92508..f8dbe8d 100644 --- a/Firmware/Firmware.ATXMEGA/SoundCard/interrupts.c +++ b/Firmware/Firmware.ATXMEGA/SoundCard/interrupts.c @@ -3,7 +3,7 @@ #include "app_ios_and_regs.h" #include "app_funcs.h" #include "hwbp_core.h" -//#include "parallel_bus.h" +#include "parallel_bus.h" /************************************************************************/ /* Declare application registers */ @@ -30,19 +30,54 @@ extern AppRegs app_regs; /************************************************************************/ /* DIN0 */ /************************************************************************/ +bool din0_previous_state = false; + +extern uint16_t last_sound_triggered; + ISR(PORTB_INT0_vect, ISR_NAKED) { + bool din0 = read_DIN0 ? true : false; - //app_regs.REG_PLAY_SOUND_OR_FREQ = 3; //default plays index 3 - //app_write_REG_PLAY_SOUND_OR_FREQ(&app_regs.REG_PLAY_SOUND_OR_FREQ); - - uint8_t aux = read_DIN0; - - app_regs.REG_DIGITAL_INPUTS = aux; - app_write_REG_DIGITAL_INPUTS(&app_regs.REG_DIGITAL_INPUTS); - core_func_send_event(ADD_REG_DIGITAL_INPUTS, true); - - par_cmd_start_sound(app_regs.REG_DI0_SOUND_INDEX, app_regs.REG_ATTNUATION_LEFT, app_regs.REG_ATTENUATION_RIGHT); + if (din0 != din0_previous_state) + { + din0_previous_state = din0; + + if (din0) + { + switch (app_regs.REG_DI0_CONF) + { + case GM_DI_SYNC: + app_regs.REG_DIGITAL_INPUTS |= B_DI0; + core_func_send_event(ADD_REG_DIGITAL_INPUTS, true); + break; + + case GM_DI_START_AND_STOP_SOUND: + case GM_DI_START_SOUND: + par_cmd_start_sound(app_regs.REG_DI0_SOUND_INDEX, app_regs.REG_DI0_ATTENUATION_LEFT, app_regs.REG_DI0_ATTENUATION_RIGHT); + /* Save the sound being played */ + last_sound_triggered = app_regs.REG_DI0_SOUND_INDEX; + break; + + case GM_DI_STOP: + par_cmd_stop(); + break; + } + } + else + { + switch (app_regs.REG_DI0_CONF) + { + case GM_DI_SYNC: + app_regs.REG_DIGITAL_INPUTS &= ~B_DI0; + core_func_send_event(ADD_REG_DIGITAL_INPUTS, true); + break; + + case GM_DI_START_AND_STOP_SOUND: + par_cmd_stop(); + break; + } + } + } reti(); } @@ -50,9 +85,54 @@ ISR(PORTB_INT0_vect, ISR_NAKED) /************************************************************************/ /* DIN1 */ /************************************************************************/ +bool din1_previous_state = false; + ISR(PORTD_INT0_vect, ISR_NAKED) { - reti(); + bool din1 = read_DIN1 ? true : false; + + if (din1 != din1_previous_state) + { + din1_previous_state = din1; + + if (din1) + { + switch (app_regs.REG_DI1_CONF) + { + case GM_DI_SYNC: + app_regs.REG_DIGITAL_INPUTS |= B_DI1; + core_func_send_event(ADD_REG_DIGITAL_INPUTS, true); + break; + + case GM_DI_START_AND_STOP_SOUND: + case GM_DI_START_SOUND: + par_cmd_start_sound(app_regs.REG_DI1_SOUND_INDEX, app_regs.REG_DI1_ATTENUATION_LEFT, app_regs.REG_DI1_ATTENUATION_RIGHT); + /* Save the sound being played */ + last_sound_triggered = app_regs.REG_DI1_SOUND_INDEX; + break; + + case GM_DI_STOP: + par_cmd_stop(); + break; + } + } + else + { + switch (app_regs.REG_DI0_CONF) + { + case GM_DI_SYNC: + app_regs.REG_DIGITAL_INPUTS &= ~B_DI1; + core_func_send_event(ADD_REG_DIGITAL_INPUTS, true); + break; + + case GM_DI_START_AND_STOP_SOUND: + par_cmd_stop(); + break; + } + } + } + + reti(); } /************************************************************************/ @@ -61,7 +141,10 @@ ISR(PORTD_INT0_vect, ISR_NAKED) /* ISR(PORTC_INT0_vect, ISR_NAKED) { - reti(); + Digital IN2 don't have interrupt because the available interrupt on + PortC is being used by the communication between ATXMEGA and PIC32. + + reti(); } */ @@ -71,4 +154,67 @@ ISR(PORTC_INT0_vect, ISR_NAKED) ISR(PORTD_INT1_vect, ISR_NAKED) { reti(); +} + + +/************************************************************************/ +/* ADC */ +/************************************************************************/ +extern int16_t AdcOffset; + +extern bool first_adc_channel; + +ISR(ADCA_CH0_vect, ISR_NAKED) +{ + if (first_adc_channel) + { + first_adc_channel = false; + + /* Read ADC */ + if (ADCA_CH0_RES > AdcOffset) + app_regs.REG_DATA_STREAM[0] = (ADCA_CH0_RES & 0x0FFF) - AdcOffset; + else + app_regs.REG_DATA_STREAM[0] = 0; + + /* Start conversation on ADCA Channel 9 */ + ADCA_CH0_MUXCTRL = 9 << 3; + ADCA_CH0_CTRL |= ADC_CH_START_bm; + } + else + { + /* Read ADC */ + if (ADCA_CH0_RES > AdcOffset) + app_regs.REG_DATA_STREAM[1] = (ADCA_CH0_RES & 0x0FFF) - AdcOffset; + else + app_regs.REG_DATA_STREAM[1] = 0; + + core_func_send_event(ADD_REG_DATA_STREAM, false); + } + + reti(); +} + +/************************************************************************/ +/* STOP CMD SENT */ +/************************************************************************/ +ISR(TCC0_OVF_vect, ISR_NAKED) +{ + core_func_send_event(ADD_REG_STOP, true); + timer_type0_stop(&TCC0); + + reti(); +} + +/************************************************************************/ +/* CLEAR DIGITAL OUTPUT */ +/************************************************************************/ +ISR(TCE0_OVF_vect, ISR_NAKED) +{ + if (app_regs.REG_DO0_CONF == GM_DO_PULSE) {clr_DOUT0;} + if (app_regs.REG_DO1_CONF == GM_DO_PULSE) {clr_DOUT1;} + if (app_regs.REG_DO2_CONF == GM_DO_PULSE) {clr_DOUT2;} + + timer_type0_stop(&TCE0); + + reti(); } \ No newline at end of file diff --git a/Firmware/Firmware.ATXMEGA/SoundCard/parallel_bus.c b/Firmware/Firmware.ATXMEGA/SoundCard/parallel_bus.c index aa81447..9bffd0d 100644 --- a/Firmware/Firmware.ATXMEGA/SoundCard/parallel_bus.c +++ b/Firmware/Firmware.ATXMEGA/SoundCard/parallel_bus.c @@ -139,16 +139,19 @@ ISR(PORTC_INT0_vect, ISR_NAKED) { if (last_sound_triggered != 0) { - app_regs.REG_PLAY_SOUND_OR_FREQ = last_sound_triggered; - core_func_send_event(ADD_REG_PLAY_SOUND_OR_FREQ, true); - last_sound_triggered = 0; // The event was sent and a new sound can be trigger - } - - //set_DOUT0; - } - else - { - //clr_DOUT0; + app_regs.REG_PLAY_SOUND_OR_FREQ = last_sound_triggered; + core_func_send_event(ADD_REG_PLAY_SOUND_OR_FREQ, true); + last_sound_triggered = 0; // The event was sent and a new sound can be trigger + } + + if (app_regs.REG_DO0_CONF == GM_DO_PULSE) {set_DOUT0;} + if (app_regs.REG_DO1_CONF == GM_DO_PULSE) {set_DOUT1;} + if (app_regs.REG_DO2_CONF == GM_DO_PULSE) {set_DOUT2;} + + /* Set timer for 400s to clear the digital output */ + /* Is can't be higher!! */ + timer_type0_enable(&TCE0, TIMER_PRESCALER_DIV64, 400/2, INT_LEVEL_LOW); + } reti(); @@ -182,7 +185,11 @@ void par_cmd_stop(void) } bool par_cmd_stop_callback (void) -{ +{ + // Measurements show that this timer equal to 476 us put all the real stops + // inside a interval of +/- 200 us + timer_type0_enable(&TCC0, TIMER_PRESCALER_DIV64, 476/2, INT_LEVEL_LOW); + send_last_byte(cmd_stop[CMD_STOP_LEN - 1]); } diff --git a/Firmware/Firmware.ATXMEGA/SoundCard/registers.xls b/Firmware/Firmware.ATXMEGA/SoundCard/registers.xls index ddaf59a..2c006da 100644 Binary files a/Firmware/Firmware.ATXMEGA/SoundCard/registers.xls and b/Firmware/Firmware.ATXMEGA/SoundCard/registers.xls differ diff --git a/device.yml b/device.yml index 67d173b..fe67de8 100644 --- a/device.yml +++ b/device.yml @@ -3,7 +3,7 @@ # yaml-language-server: $schema=https://harp-tech.org/draft-02/schema/device.json device: SoundCard whoAmI: 1280 -firmwareVersion: "2.2" +firmwareVersion: "3.0" hardwareTargets: "1.1" registers: PlaySoundOrFrequency: &frequency @@ -14,8 +14,8 @@ registers: Stop: address: 33 type: U8 - access: Write - description: Any value will stop the current sound + access: [Write, Event] + description: Any value will stop the frequency generation (not implemented for a sound index). The time precision of this event it frequency dependent. It's +/- 2500 us at 500 Hz, +/- 750 us at 1000 Hz, +/- 250 us at 2000 Hz and bellow +/- 210 us for any frequency above 5000 Hz. AttenuationLeft: &attenuation address: 34 type: U16 @@ -29,12 +29,12 @@ registers: <<: *attenuation address: 36 length: 2 - description: Configures both attenuation on right and left channels [Att R] [Att L] + description: Configures both attenuation on right and left channels [Att R] [Att L] (1 LSB is 0.1dB) AttenuationAndPlaySoundOrFreq: <<: *attenuation address: 37 length: 3 - description: Configures attenuation and plays sound index [Att R] [Att L] [Index] + description: Configures attenuation and plays sound index or frequency [Att R] [Att L] [Index] Reserved0: &reserved address: 38 type: U8 @@ -60,172 +60,99 @@ registers: <<: *configureDI address: 42 description: Configuration of the digital input 1 (DI1) - ConfigureDI2: - <<: *configureDI + SoundOrFrequencyDI0: &soundIndex address: 43 - description: Configuration of the digital input 2 (DI2) - SoundIndexDI0: &soundIndex - address: 44 - type: U8 + type: U16 access: Write description: Specifies the sound index to be played when triggering DI0 - SoundIndexDI1: + SoundOrFrequencyDI1: <<: *soundIndex - address: 45 + address: 44 description: Specifies the sound index to be played when triggering DI1 - SoundIndexDI2: - <<: *soundIndex - address: 46 - description: Specifies the sound index to be played when triggering DI2 - FrequencyDI0: - <<: *frequency - address: 47 - description: Specifies the sound frequency to be played when triggering DI0 - FrequencyDI1: - <<: *frequency - address: 48 - description: Specifies the sound frequency to be played when triggering DI1 - FrequencyDI2: - <<: *frequency - address: 49 - description: Specifies the sound frequency to be played when triggering DI2 AttenuationLeftDI0: <<: *attenuation - address: 50 - description: Left channel's attenuation (1 LSB is 0.5dB) when triggering DI0 + address: 45 + description: Left channel's attenuation (1 LSB is 0.1dB) when triggering DI0 AttenuationLeftDI1: <<: *attenuation - address: 51 - description: Left channel's attenuation (1 LSB is 0.5dB) when triggering DI1 - AttenuationLeftDI2: - <<: *attenuation - address: 52 - description: Left channel's attenuation (1 LSB is 0.5dB) when triggering DI2 + address: 46 + description: Left channel's attenuation (1 LSB is 0.1dB) when triggering DI1 AttenuationRightDI0: <<: *attenuation - address: 53 - description: Right channel's attenuation (1 LSB is 0.5dB) when triggering DI0 + address: 47 + description: Right channel's attenuation (1 LSB is 0.1dB) when triggering DI0 AttenuationRightDI1: <<: *attenuation - address: 54 - description: Right channel's attenuation (1 LSB is 0.5dB) when triggering DI1 - AttenuationRightDI2: - <<: *attenuation - address: 55 - description: Right channel's attenuation (1 LSB is 0.5dB) when triggering DI2 - AttenuationAndSoundIndexDI0: - <<: *attenuation - address: 56 - length: 3 - description: Sound index and attenuation to be played when triggering DI0 [Att R] [Att L] [Index] - AttenuationAndSoundIndexDI1: - <<: *attenuation - address: 57 - length: 3 - description: Sound index and attenuation to be played when triggering DI1 [Att R] [Att L] [Index] - AttenuationAndSoundIndexDI2: - <<: *attenuation - address: 58 - length: 3 - description: Sound index and attenuation to be played when triggering DI2 [Att R] [Att L] [Index] - AttenuationAndFrequencyDI0: - <<: *attenuation - address: 59 - length: 2 - description: Sound index and attenuation to be played when triggering DI0 [Att BOTH] [Frequency] - AttenuationAndFrequencyDI1: - <<: *attenuation - address: 60 - length: 2 - description: Sound index and attenuation to be played when triggering DI1 [Att BOTH] [Frequency] - AttenuationAndFrequencyDI2: - <<: *attenuation - address: 61 - length: 2 - description: Sound index and attenuation to be played when triggering DI2 [Att BOTH] [Frequency] + address: 48 + description: Right channel's attenuation (1 LSB is 0.1dB) when triggering DI1 Reserved2: <<: *reserved - address: 62 + address: 49 Reserved3: <<: *reserved - address: 63 + address: 50 Reserved4: <<: *reserved - address: 64 + address: 51 ConfigureDO0: &configureDO - address: 65 + address: 52 type: U8 access: Write maskType: DigitalOutputConfiguration description: Configuration of the digital output 0 (DO0) ConfigureDO1: <<: *configureDO - address: 66 + address: 53 description: Configuration of the digital output 1 (DO1) ConfigureDO2: <<: *configureDO - address: 67 - description: Configuration of the digital output 2 (DO2 - PulseDO0: &pulseDO - address: 68 - type: U8 - access: Write - minValue: 1 - maxValue: 255 - description: Pulse for the digital output 0 (DO0) - PulseDO1: - <<: *pulseDO - address: 69 - description: Pulse for the digital output 1 (DO1) - PulseDO2: - <<: *pulseDO - address: 70 - description: Pulse for the digital output 2 (DO2) + address: 54 + description: Configuration of the digital output 2 (DO2) Reserved5: <<: *reserved - address: 71 + address: 55 Reserved6: <<: *reserved - address: 72 + address: 56 Reserved7: <<: *reserved - address: 73 + address: 57 OutputSet: &output - address: 74 + address: 58 type: U8 access: Write maskType: DigitalOutputs description: Set the specified digital output lines OutputClear: <<: *output - address: 75 + address: 59 description: Clear the specified digital output lines OutputToggle: <<: *output - address: 76 + address: 60 description: Toggle the specified digital output lines OutputState: <<: *output - address: 77 + address: 61 description: Write the state of all digital output lines Reserved8: <<: *reserved - address: 78 + address: 62 Reserved9: <<: *reserved - address: 79 - ConfigureAdc: - address: 80 + address: 63 + EnableDataStream: + address: 64 type: U8 access: Write - maskType: AdcConfiguration - description: Configuration of Analog Inputs - AnalogData: - address: 81 + maskType: DataStreamConfiguration + description: Configuration of the data stream + DataStream: + address: 65 type: U16 access: Event length: 5 - description: Contains sampled analog input data or dynamic sound parameters controlled by the ADC channels. Values are zero if not used. + description: Contains sampled analog input data and sound parameters. payloadSpec: Adc0: offset: 0 @@ -235,87 +162,122 @@ registers: description: The sampled analog input value on ADC1. AttenuationLeft: offset: 2 - description: The amplitude of the left channel controlled by ADC0. + description: The current amplitude of the left channel. AttenuationRight: offset: 3 - description: The amplitude of the right channel controlled by ADC0. + description: The current amplitude of the right channel. Frequency: offset: 4 - description: The output frequency controlled by ADC1. - Commands: - address: 82 + description: The output sound index (if less than 32) or frequency (if greater or equal than 32) being played. + ConfigureAdc0: + address: 66 type: U8 access: Write - maskType: ControllerCommand - description: Send commands to PIC32 micro-controller + maskType: Adc0Configuration + visibility: private + description: Configuration of analog input ADC0 (not implemented yet) + ConfigureAdc1: + address: 67 + type: U8 + access: Write + maskType: Adc1Configuration + visibility: private + description: Configuration of analog input ADC1 (not implemented yet) Reserved10: <<: *reserved - address: 83 + address: 68 Reserved11: <<: *reserved - address: 84 + address: 69 Reserved12: <<: *reserved - address: 85 - EnableEvents: - address: 86 + address: 70 + Reserved13: + <<: *reserved + address: 71 + Reserved14: + <<: *reserved + address: 72 + Reserved15: + <<: *reserved + address: 73 + Reserved16: + <<: *reserved + address: 74 + Reserved17: + <<: *reserved + address: 75 + Reserved18: + <<: *reserved + address: 76 + Reserved19: + <<: *reserved + address: 77 + Reserved20: + <<: *reserved + address: 78 + Reserved21: + <<: *reserved + address: 79 + Reserved22: + <<: *reserved + address: 80 + Reserved23: + <<: *reserved + address: 81 + Commands: + address: 82 type: U8 access: Write - maskType: SoundCardEvents - description: Specifies the active events in the SoundCard device + maskType: ControllerCommand + description: Send commands to PIC32 micro-controller bitMasks: DigitalInputs: description: Specifies the state of the digital input lines. bits: - DI0: 0x1 + DI0: {value: 1, description: Digital input 0.} + DI1: {value: 2, description: Digital input 1.} + DI2: {value: 4, description: Digital input 2 (don't have associated event).} DigitalOutputs: description: Specifies the state of the digital output lines. bits: - DO0: 0x1 - DO1: 0x2 - DO2: 0x3 - SoundCardEvents: - description: Specifies the active events in the SoundCard. - bits: - PlaySoundOrFrequency: 0x1 - Stop: 0x2 - DigitalInputs: 0x4 - AdcValues: 0x8 + DO0: {value: 1, description: Digital output 0.} + DO1: {value: 2, description: Digital output 1.} + DO2: {value: 4, description: Digital output 2.} groupMasks: DigitalInputConfiguration: description: Specifies the operation mode of the digital input. values: Digital: {value: 0, description: Used as a pure digital input.} - StartAndStopSound: {value: 1, description: Starts sound when rising edge and stop when falling edge.} - StartSound: {value: 2, description: Starts sound when rising edge.} - Stop: {value: 3, description: Stops sound or frequency when rising edge.} - StartAndStopFrequency: {value: 4, description: Starts frequency when rising edge and stop when falling edge.} - StartFrequency: {value: 5, description: Starts frequency when rising edge.} + StartAndStopSound: {value: 1, description: Starts sound index (if less than 32) or frequency (if greater or equal than 32) when rising edge and stop when falling edge (frequency only).} + StartSound: {value: 2, description: Starts sound index (if less than 32) or frequency (if greater or equal than 32) when rising edge.} + StopSound: {value: 3, description: Stops frequency when rising edge.} DigitalOutputConfiguration: description: Specifies the operation mode of the digital output. values: Digital: {value: 0, description: Used as a pure digital output.} - Pulse: {value: 1, description: The digital output will be high during a period specified by register DOxPulse.} - HighWhenSound: {value: 2, description: High when the sound is being played. } - Pulse1MsWhenStart: {value: 3, description: High when sound starts during 1 ms. } - Pulse10MsWhenStart: {value: 4, description: High when sound starts during 10 ms. } - Pulse100MsWhenStart: {value: 5, description: High when sound starts during 100 ms. } - Pulse1MsWhenStop: {value: 6, description: High when sound stops during 1 ms. } - Pulse10MsWhenStop: {value: 7, description: High when sound stops during 10 ms. } - Pulse100MsWhenStop: {value: 8, description: High when sound starts during 100 ms. } + PulseForSoundStartOrFrequencyChange: {value: 1, description: Positive 500us pulse of when sound starts or frequency changes. } + DataStreamConfiguration: + description: Specifies the operation mode of the data stream. + values: + Disabled: 0 + StreamAt1Khz: 1 + Adc0Configuration: + description: Specifies the operation mode of the analog input ADC0. + values: + AnalogInputOnly: 0 + ControlsLeftChannelAmplitude: 1 + ControlsBothChannelsAmplitude: 2 + Adc1Configuration: + description: Specifies the operation mode of the analog input ADC1. + values: + AnalogInputOnly: 0 + ControlsRightChannelAmplitude: 1 + ControlsBothChannelsAmplitude: 2 + ControlsFrequencyGenerator: 3 ControllerCommand: description: Specifies commands to send to the PIC32 micro-controller values: DisableBootloader: 0 EnableBootloader: 1 DeleteAllSounds: 255 - AdcConfiguration: - description: Specifies the operation mode of the analog inputs. - values: - NotUsed: 0 - AdcAdc: 1 - AmplitudeBothAdc: 2 - AmplitudeLeftAdc: 3 - AmplitudeRightAdc: 4 - AmplitudeLeftAmplitudeRight: 5 - AmplitudeBothFrequency: 6 \ No newline at end of file