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v3.0 firmware release #20

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c9d3e1e
Removed not used registers and updated registers' description.
filcarv May 2, 2024
f88154a
Removed more not used registers and created ADCx_CONF.
filcarv May 3, 2024
bd5c6e8
Moved register REG_COMMANDS to position 82.
filcarv May 3, 2024
a3658d1
Added read of the digital inputs.
filcarv Jun 20, 2024
0bf9d52
Implemented digital input interrupts.
filcarv Jun 20, 2024
aad5de5
Changed registers to U16
filcarv Jun 20, 2024
34e1c1c
Correct digital output configuration.
filcarv Jun 20, 2024
63bb007
Minor correction and protect writing to the data stream register.
filcarv Jun 20, 2024
fce891d
Implemented the data stream.
filcarv Jun 20, 2024
4c251ee
Moved ADC readings into interrupts.
filcarv Jun 20, 2024
2220102
Implemented the stop command.
filcarv Jun 20, 2024
bf5e03a
Added pulse to digital outputs and implemented defaults.
filcarv Jun 20, 2024
d5a3d21
Fixed START event when sent from digital inputs.
filcarv Jun 20, 2024
6ac52be
Stop frequency when goes to standby. Fix #5.
filcarv Jun 20, 2024
166b2d7
Correct SoundOrFrequency type
artursilva0 Jul 9, 2024
784ffa2
Fix digital outputs
artursilva0 Jul 9, 2024
113660f
Merge pull request #21 from harp-tech/bug_correction_fw-clean_registers-
artursilva0 Jul 9, 2024
e71d2b3
Correct typos
bruno-f-cruz Jul 11, 2024
3baf342
Remove default value that causes generator to fail when casting to Enum
bruno-f-cruz Jul 11, 2024
189a0d6
Make not implemented registers private
bruno-f-cruz Jul 11, 2024
7c0cff1
Add pulse duration information
bruno-f-cruz Jul 11, 2024
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75 changes: 49 additions & 26 deletions Firmware/Firmware.ATXMEGA/SoundCard/app.c
Original file line number Diff line number Diff line change
Expand Up @@ -22,15 +22,15 @@ extern bool (*app_func_wr_pointer[])(void*);
/************************************************************************/
static const uint8_t default_device_name[] = "SoundCard";

#define MAJOR_FW_VERSION 2
#define MAJOR_FW_VERSION 3

void hwbp_app_initialize(void)
{
/* Define versions */
uint8_t hwH = 2;
uint8_t hwL = 2;
uint8_t fwH = MAJOR_FW_VERSION;
uint8_t fwL = 2;
uint8_t fwL = 0;
uint8_t ass = 0;

/* Start core */
Expand Down Expand Up @@ -158,9 +158,31 @@ void core_callback_initialize_hardware(void)
ADCA_CH0_CTRL |= ADC_CH_START_bm; // Force the first conversion
while(!(ADCA_CH0_INTFLAGS & ADC_CH_CHIF_bm)); // Wait for conversion to finish
ADCA_CH0_INTFLAGS = ADC_CH_CHIF_bm; // Clear interrupt bit

ADCA_CH0_INTCTRL |= ADC_CH_INTLVL_LO_gc; // Enable ADC0 interrupt
}

void core_callback_reset_registers(void) {}
void core_callback_reset_registers(void)
{
app_regs.REG_DI0_CONF = GM_DI_SYNC;
app_regs.REG_DI1_CONF = GM_DI_SYNC;

app_regs.REG_DI0_SOUND_INDEX = 2000; // 2 KHz
app_regs.REG_DI1_SOUND_INDEX = 4000; // 4 KHz
app_regs.REG_DI0_ATTENUATION_LEFT = 60; // -6 DFS
app_regs.REG_DI1_ATTENUATION_LEFT = 60; // -6 DFS
app_regs.REG_DI0_ATTENUATION_RIGHT = 60; // -6 DFS
app_regs.REG_DI1_ATTENUATION_RIGHT = 60; // -6 DFS

app_regs.REG_DO0_CONF = GM_DO_PULSE;
app_regs.REG_DO1_CONF = GM_DO_DIG;
app_regs.REG_DO2_CONF = GM_DO_DIG;

app_regs.REG_DATA_STREAM_CONF = GM_DATA_STREAM_OFF;

app_regs.REG_ADC0_CONF = GM_ADC0_PURE_ANALOG_INPUT;
app_regs.REG_ADC1_CONF = GM_ADC1_PURE_ANALOG_INPUT;
}

void core_callback_registers_were_reinitialized(void) {}

Expand All @@ -181,41 +203,42 @@ void core_callback_visualen_to_off(void)
/************************************************************************/
/* Callbacks: Change on the operation mode */
/************************************************************************/
void core_callback_device_to_standby(void) {}
extern uint16_t last_sound_triggered;

void core_callback_device_to_standby(void)
{
par_cmd_stop();
last_sound_triggered = 0;
}
void core_callback_device_to_active(void) {}
void core_callback_device_to_enchanced_active(void) {}
void core_callback_device_to_enhanced_active(void) {}
void core_callback_device_to_speed(void) {}

/************************************************************************/
/* Callbacks: 1 ms timer */
/************************************************************************/
bool first_adc_channel;

void core_callback_t_before_exec(void) {}
void core_callback_t_after_exec(void) {}
void core_callback_t_new_second(void) {}
void core_callback_t_500us(void) {}
void core_callback_t_1ms(void)
{
/* Read ADC0 */
ADCA_CH0_MUXCTRL = 10 << 3; // Select pin
ADCA_CH0_CTRL |= ADC_CH_START_bm; // Start conversion
while(!(ADCA_CH0_INTFLAGS & ADC_CH_CHIF_bm)); // Wait for conversion to finish
ADCA_CH0_INTFLAGS = ADC_CH_CHIF_bm; // Clear interrupt bit
if (ADCA_CH0_RES > AdcOffset)
app_regs.REG_ADC_VALUES[0] = (ADCA_CH0_RES & 0x0FFF) - AdcOffset;
else
app_regs.REG_ADC_VALUES[0] = 0;

/* Read ADC1 */
ADCA_CH0_MUXCTRL = 9 << 3; // Select pin
ADCA_CH0_CTRL |= ADC_CH_START_bm; // Start conversion
while(!(ADCA_CH0_INTFLAGS & ADC_CH_CHIF_bm)); // Wait for conversion to finish
ADCA_CH0_INTFLAGS = ADC_CH_CHIF_bm; // Clear interrupt bit
if (ADCA_CH0_RES > AdcOffset)
app_regs.REG_ADC_VALUES[1] = (ADCA_CH0_RES & 0x0FFF) - AdcOffset;
else
app_regs.REG_ADC_VALUES[1] = 0;

//core_func_send_event(ADD_REG_ADC_VALUES, true);
if (app_regs.REG_DATA_STREAM_CONF == GM_DATA_STREAM_1KHz)
{
/* Read ADC */
core_func_mark_user_timestamp();

app_regs.REG_DATA_STREAM[2] = app_regs.REG_SET_ATTENUATION_AND_PLAY_SOUND_OR_FREQ[1];
app_regs.REG_DATA_STREAM[3] = app_regs.REG_SET_ATTENUATION_AND_PLAY_SOUND_OR_FREQ[2];
app_regs.REG_DATA_STREAM[4] = app_regs.REG_SET_ATTENUATION_AND_PLAY_SOUND_OR_FREQ[0];

/* Start conversation on ADCA Channel 10 */
first_adc_channel = true;
ADCA_CH0_MUXCTRL = 10 << 3;
ADCA_CH0_CTRL |= ADC_CH_START_bm;
}
}

/************************************************************************/
Expand Down
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