urukul/v1.3 changes: add osc_en_n and mmcx_osc_sel

* tp3 and tp4 connected to mmcx_osc_sel and osc_en_n in hardware
hartytp · Oct 5, 2018 · bc43806 · bc43806
1 parent 2d1c145
commit bc43806
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Showing 2 changed files with 15 additions and 13 deletions.
diff --git a/urukul.py b/urukul.py
@@ -2,7 +2,7 @@
 
 
 # increment this if the behavior (LEDs, registers, EEM pins) changes
-__proto_rev__ = 8
+__proto_rev__ = 9
 
 
 class SR(Module):
@@ -73,14 +73,14 @@ class CFG(Module):
     | RF_SW     | 4     | Activates RF switch per channel                 |
     | LED       | 4     | Activates the red LED per channel               |
     | PROFILE   | 3     | Controls DDS[0:3].PROFILE[0:2]                  |
-    | DUMMY     | 1     |                                                 |
+    | CLK_SEL1  | 1     | Selects CLK source: 0 OSC, 1 MMCX               |
     | IO_UPDATE | 1     | Asserts DDS[0:3].IO_UPDATE where CFG.MASK_NU    |
     |           |       | is high                                         |
     | MASK_NU   | 4     | Disables DDS from QSPI interface, disables      |
     |           |       | IO_UPDATE control through IO_UPDATE EEM signal, |
     |           |       | enables access through CS=3, enables control of |
     |           |       | IO_UPDATE through CFG.IO_UPDATE                 |
-    | CLK_SEL   | 1     | Selects CLK source                              |
+    | CLK_SEL0  | 1     | Selects CLK source: 0 MMCX/OSC, 1 SMA           |
     | SYNC_SEL  | 1     | Selects SYNC source                             |
     | RST       | 1     | Asserts DDS[0:3].RESET, DDS[0:3].MASTER_RESET,  |
     |           |       | ATT[0:3].RST                                    |
@@ -93,12 +93,12 @@ def __init__(self, platform, n=4):
 
             ("profile", 3),
 
-            ("dummy", 1),
+            ("clk_sel1", 1),
             ("io_update", 1),
 
             ("mask_nu", 4),
 
-            ("clk_sel", 1),
+            ("clk_sel0", 1),
             ("sync_sel", 1),
 
             ("rst", 1),
@@ -112,7 +112,9 @@ def __init__(self, platform, n=4):
 
         self.comb += [
                 dds_common.profile.eq(self.data.profile),
-                clk.in_sel.eq(self.data.clk_sel),
+                clk.in_sel.eq(self.data.clk_sel0),
+                clk.mmcx_osc_sel.eq(self.data.clk_sel1),
+                clk.osc_en_n.eq(clk.in_sel | clk.mmcx_osc_sel),
                 dds_sync.sync_sel.eq(self.data.sync_sel),
                 dds_common.master_reset.eq(self.data.rst),
                 dds_common.io_reset.eq(self.data.io_rst),
@@ -471,11 +473,9 @@ def __init__(self, platform):
                         cfg.data.io_update, eem[6].i)),
             ]
 
-        tp = [platform.request("tp", i) for i in range(5)]
+        tp = [platform.request("tp", i) for i in range(3)]
         self.comb += [
                 tp[0].eq(dds[0].cs_n),
                 tp[1].eq(dds[0].sck),
-                tp[2].eq(dds[0].sdo),
-                tp[3].eq(dds[0].sdi),
-                tp[4].eq(sr.cd_le.clk)
+                tp[2].eq(dds[0].sdo)
         ]
diff --git a/urukul_cpld.py b/urukul_cpld.py
@@ -6,8 +6,8 @@
         ("tp", 0, Pins("P143")),
         ("tp", 1, Pins("P140")),
         ("tp", 2, Pins("P138")),
-        ("tp", 3, Pins("P136")),
-        ("tp", 4, Pins("P134")),
+        # ("tp", 3, Pins("P136")),  # mmcx_osc_sel
+        # ("tp", 4, Pins("P134")),  # osc_en_n
 
         # P112 is open on Urukul/v1.0
         ("ifc_mode", 0, Pins("P104 P105 P110 P112")),
@@ -22,7 +22,9 @@
 
         ("clk", 0,
             Subsignal("div", Pins("P11")),
-            Subsignal("in_sel", Pins("P12"))),
+            Subsignal("in_sel", Pins("P12")),
+            Subsignal("mmcx_osc_sel", Pins("P136")),
+            Subsignal("osc_en_n", Pins("P134"))),
 
         ("att", 0,
             Subsignal("clk", Pins("P95")),