GitHub - hcyang99/rv32-core: Arbitary superscalar out-of-order RV32I core, with instruction prefetching and write-back no-write-allocate DCache.

hcyang99 / rv32-core Public

Notifications You must be signed in to change notification settings
Fork 2
Star 4

Arbitary superscalar out-of-order RV32I core, with instruction prefetching and write-back no-write-allocate DCache.

Notifications

Name		Name	Last commit message	Last commit date
Latest commit History 381 Commits
module_provided		module_provided
script		script
synth		synth
test_progs		test_progs
testbench		testbench
verilog		verilog
.gitignore		.gitignore
ISA.svh		ISA.svh
Makefile		Makefile
README.txt		README.txt
run-master.sh		run-master.sh
run_syn.sh		run_syn.sh
run_test.sh		run_test.sh
sys_defs.svh		sys_defs.svh

Repository files navigation

EECS 470 BEST PERFORMING PROJECT WN2020
Group Members: Alvin Bahri, Haichao Yang, Wesley Shen, Yiqiu Sun, Yongle Liu

Arbitary superscalar out-of-order RV32I core, with instruction prefetching and write-back no-write-allocate DCache.

Only 16-bit memory address space used. Floating point not implemented.

See Makefile for usage. Requires VCS etc. to simulate.

Number of superscalar ways can be changed via the `WAYS macro in sys_defs.svh. Currently 3. Tested for 2-8. It is known to be not working with `WAYS == 1.