Problem with implemantation of csi2_rx core

[geimel]

Hello hellgate,
thank you for sharing your csi core here.
I've copied the core in my design which uses the zynq 7020 module from enclustra, with clg484 package.
So the hardware is nearly the same that you have used, only the used pins are different.
I have some problems while implementing the design, vivado give me an error, but I cannot find the problem.
Perhaps you have an idea how to solve this.
[Vivado 12-1411] Cannot set LOC property of ports, Could not legally place instance cpu_i/Sensor_A/csi2_2_lane_rx_0/inst/csi2_rx/phy/clk_phy/clk_diff_input at G15 (IOB_X1Y142) since it belongs to a shape containing instance cpu_i/Sensor_A/csi2_2_lane_rx_0/inst/csi2_rx/phy/clk_phy/clk_buf. The shape requires relative placement between cpu_i/Sensor_A/csi2_2_lane_rx_0/inst/csi2_rx/phy/clk_phy/clk_diff_input and cpu_i/Sensor_A/csi2_2_lane_rx_0/inst/csi2_rx/phy/clk_phy/clk_buf that can not be honoured because it would result in an invalid location for cpu_i/Sensor_A/csi2_2_lane_rx_0/inst/csi2_rx/phy/clk_phy/clk_buf. ["E:/Xilinx/Vivado_projects/MarsBB1.1_PI_V2_2019.1/mars_BB1.1/gvrd/gvrd.srcs/constrs_1/new/IMX219_PI_CAM_V2.xdc":74]

Thank you very much
Richard

[hellgate202]

Hi Richard, sorry for a long wait.
It appears that Vivado is struggling to instantiate differential buffer and an IO buffer at the same time.
What I can suggest: try the Vivado version 2018.3, which this project was lastly build for or try imx477 branch version of the clock phy, it contains other options like mmcm compensation, which may accidentally fix your issue