Asymmetric PWM + DMA

[sadkotheguest]

Could you tell - is it possible to use the DMA module for updating 2 (or more) registers to generate the waveform with pre-calculated coefficients stored in the RAM? When I am using the asymmetric PWM - I need to update several registers to change the output waveform.

According to HPM6200_UM_V1_0 (34.2.14):

PWM 定时器支持生成以下 DMA 请求：
● RLD 当重载事件产生时，即计数器计数达到重载寄存器值，或者由同步触发输入 SYNCI 引发计数器重载
● XRLD：当扩展计数器扩展计数位计数至扩展重载计数位时，该位置 1，或者由 SYNCI 将计数器重置时
● HALFRLD：当计数器计数至起始寄存器到重载寄存器的中间时
● 当比较器设置为输出比较，发生匹配事件时
● 当比较器设置为输入捕获，并在输入通道捕获到指定边沿跳变时

The PWM timer supports the generation of the following DMA requests：
● RLD When an overloading event occurs, that is, the counter count reaches the overloading register value, or the counter overloading is triggered by the synchronization trigger input SYNCI.
● XRLD: When the extended counter extends the count bit to the extended overload count bit, this position is 1, or when the counter is reset by SYNCI
● HALFRLD: When the counter counts to the middle of the start register to the overload register
● When the comparator is set to output comparison and a matching event occurs
● When the comparator is set to input capture and the input channel captures the specified edge transition

So:

1. Does it mean that i can use every of 24 CMP registers to generate the DMA event to update PWM registers?
2. Are there any issues with shadow registers when the DMA module is using?
3. Is it possible to update several PWM registers (i.e. several CMP registers or RLD) with one DMA transaction?

[willChuai]

1.yes
2.Requires a hardware trigger to update shadow registers
3.CMP is easier to implement, just move a block of memory space. RLD requires the use of DMA chain transfers.

[sadkotheguest]

How should I setup the DMA to use the PWM_CMPxx as a trigger?

1. Set the TRGMn_DMA MUX SOURCE for the correct CMP channel.
2. Set the flag CMPENX in the DMAEN register (0x22C).
3. Do I need to setup the DMAMUX (MOTn_0...MOTn_3) and what is the the relationship between the channel TRGMn output and DMA MUX number (table 163: DMA MUX)?

^^^ is it the right sequence?

[willChuai]

You can refer to this code:

• line1
• line2

I took out the important parts:

pwm_enable_dma_request(TEST_MOTOR_PWM_BASE, PWM_IRQ_CMP(TEST_MOTOR_PWM_CAP_CMP_CHN));
dmamux_config(PLA_TMGW_DMA_LINK_DMAMUX, PLA_TMGW_DMA_LINK_DMAMUX_CH, PLA_TMGW_DMA_LINK_DMA_REQ, true);
trgm_dma_request_config(PLA_TMGW_DMA_LINK_TRGM, TRGM_DMACFG_2, TEST_MOTOR_PWM_CAP_REFRESH_DMA_LINK_CMP);

[sadkotheguest]

Thank you for the reference.