Merge pull request #247 from Treece-Burgess/09-17-2024-libpfm4-update

Update libpfm4 to Last Six of Commit ID 16cd28
icl-utk-edu · Sep 25, 2024 · 1a1ee80 · 1a1ee80
2 parents 7c6281e + 9855de3
commit 1a1ee80
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diff --git a/src/libpfm4/README b/src/libpfm4/README
@@ -78,12 +78,13 @@ The library supports many PMUs. The current version can handle:
 		ARMV7 Cortex A8
 		ARMV7 Cortex A9
 		ARMV7 Cortex A15
-		ARMV8 Cortex A57, A53, A72
+		ARMV8 Cortex A57, A53, A55, A72, A76
 		Applied Micro X-Gene
 		Qualcomm Krait
 		Fujitsu A64FX
 		Arm Neoverse V1
 		Arm Neoverse V2
+		Arm Neoverse V3
 		Huawei HiSilicon Kunpeng 920
 
 	- For SPARC

diff --git a/src/libpfm4/docs/Makefile b/src/libpfm4/docs/Makefile
@@ -146,27 +146,33 @@ ARCH_MAN += libpfm_arm_xgene.3 \
 	    libpfm_arm_ac7.3 \
 	    libpfm_arm_ac57.3 \
 	    libpfm_arm_ac53.3 \
+	    libpfm_arm_ac55.3 \
 	    libpfm_arm_ac72.3 \
+	    libpfm_arm_ac76.3 \
 	    libpfm_arm_ac15.3 \
 	    libpfm_arm_ac8.3 \
 	    libpfm_arm_ac9.3 \
 	    libpfm_arm_qcom_krait.3 \
 	    libpfm_arm_neoverse_n1.3 \
 	    libpfm_arm_neoverse_n2.3 \
-		libpfm_arm_neoverse_v1.3 \
-		libpfm_arm_neoverse_v2.3
+	    libpfm_arm_neoverse_v1.3 \
+	    libpfm_arm_neoverse_v2.3 \
+	    libpfm_arm_neoverse_v3.3
 endif
 
 ifeq ($(CONFIG_PFMLIB_ARCH_ARM64),y)
 ARCH_MAN += libpfm_arm_xgene.3 \
 	    libpfm_arm_ac57.3 \
 	    libpfm_arm_ac53.3 \
+	    libpfm_arm_ac55.3 \
 	    libpfm_arm_ac72.3 \
+	    libpfm_arm_ac76.3 \
 	    libpfm_arm_a64fx.3 \
-		libpfm_arm_neoverse_n1.3 \
+	    libpfm_arm_neoverse_n1.3 \
 	    libpfm_arm_neoverse_n2.3 \
-		libpfm_arm_neoverse_v1.3 \
-		libpfm_arm_neoverse_v2.3
+	    libpfm_arm_neoverse_v1.3 \
+	    libpfm_arm_neoverse_v2.3 \
+	    libpfm_arm_neoverse_v3.3
 endif
 
 ifeq ($(CONFIG_PFMLIB_ARCH_MIPS),y)

diff --git a/src/libpfm4/docs/man3/libpfm_arm_ac55.3 b/src/libpfm4/docs/man3/libpfm_arm_ac55.3
@@ -0,0 +1,36 @@
+.TH LIBPFM 3  "September, 2024" "" "Linux Programmer's Manual"
+.SH NAME
+libpfm_arm_ac55 - support for ARM Cortex A55 PMU
+.SH SYNOPSIS
+.nf
+.B #include <perfmon/pfmlib.h>
+.sp
+.B PMU name: arm_ac55
+.B PMU desc: ARM Cortex A55
+.sp
+.SH DESCRIPTION
+The library supports the ARM Cortex A55 core PMU.
+
+This PMU supports 6 counters and privilege levels filtering.
+It can operate in both 32 and 64 bit modes.
+
+.SH MODIFIERS
+The following modifiers are supported on ARM Cortex A55:
+.TP
+.B u
+Measure at the user level. This corresponds to \fBPFM_PLM3\fR.
+This is a boolean modifier.
+.TP
+.B k
+Measure at the kernel level. This corresponds to \fBPFM_PLM0\fR.
+This is a boolean modifier.
+.TP
+.B hv
+Measure at the hypervisor level. This corresponds to \fBPFM_PLMH\fR.
+This is a boolean modifier.
+
+.SH AUTHORS
+.nf
+Stephane Eranian <eranian@gmail.com>
+.if
+.PP
diff --git a/src/libpfm4/docs/man3/libpfm_arm_ac76.3 b/src/libpfm4/docs/man3/libpfm_arm_ac76.3
@@ -0,0 +1,36 @@
+.TH LIBPFM 3  "September, 2024" "" "Linux Programmer's Manual"
+.SH NAME
+libpfm_arm_ac76 - support for Arm Cortex A76 PMU
+.SH SYNOPSIS
+.nf
+.B #include <perfmon/pfmlib.h>
+.sp
+.B PMU name: arm_ac76
+.B PMU desc: ARM Cortex A76
+.sp
+.SH DESCRIPTION
+The library supports the ARM Cortex A76 core PMU.
+
+This PMU supports 6 counters and privilege levels filtering.
+It can operate in both 32 and 64 bit modes.
+
+.SH MODIFIERS
+The following modifiers are supported on ARM Cortex A76:
+.TP
+.B u
+Measure at the user level. This corresponds to \fBPFM_PLM3\fR.
+This is a boolean modifier.
+.TP
+.B k
+Measure at the kernel level. This corresponds to \fBPFM_PLM0\fR.
+This is a boolean modifier.
+.TP
+.B hv
+Measure at the hypervisor level. This corresponds to \fBPFM_PLMH\fR.
+This is a boolean modifier.
+
+.SH AUTHORS
+.nf
+Stephane Eranian <eranian@gmail.com>
+.if
+.PP
diff --git a/src/libpfm4/docs/man3/libpfm_arm_neoverse_v3.3 b/src/libpfm4/docs/man3/libpfm_arm_neoverse_v3.3
@@ -0,0 +1,36 @@
+.TH LIBPFM 3  "September, 2024" "" "Linux Programmer's Manual"
+.SH NAME
+libpfm_arm_neoverse_v3 - support for Arm Neoverse V3 core PMU
+.SH SYNOPSIS
+.nf
+.B #include <perfmon/pfmlib.h>
+.sp
+.B PMU name: arm_v3
+.B PMU desc: Arm Neoverse V3
+.sp
+.SH DESCRIPTION
+The library supports the Arm Neoverse V3 core PMU.
+
+This PMU supports 6 counters and privilege levels filtering.
+It can operate in both 32 and 64 bit modes.
+
+.SH MODIFIERS
+The following modifiers are supported on Arm Neoverse V3:
+.TP
+.B u
+Measure at the user level. This corresponds to \fBPFM_PLM3\fR.
+This is a boolean modifier.
+.TP
+.B k
+Measure at the kernel level. This corresponds to \fBPFM_PLM0\fR.
+This is a boolean modifier.
+.TP
+.B hv
+Measure at the hypervisor level. This corresponds to \fBPFM_PLMH\fR.
+This is a boolean modifier.
+
+.SH AUTHORS
+.nf
+Stephane Eranian <eranian@gmail.com>
+.if
+.PP
diff --git a/src/libpfm4/include/perfmon/pfmlib.h b/src/libpfm4/include/perfmon/pfmlib.h
@@ -816,6 +816,9 @@ typedef enum {
 	PFM_PMU_AMD64_FAM1AH_ZEN5_L3,	/* AMD64 Fam1Ah Zen5 L3 */
 
 	PFM_PMU_ARM_CORTEX_A72,		/* ARM Cortex A72 (ARMv8) */
+	PFM_PMU_ARM_V3,			/* Arm Neoverse V3 (ARMv9) */
+	PFM_PMU_ARM_CORTEX_A55,		/* ARM Cortex A55 (ARMv8) */
+	PFM_PMU_ARM_CORTEX_A76,		/* ARM Cortex A76 (ARMv8) */
 	/* MUST ADD NEW PMU MODELS HERE */
 
 	PFM_PMU_MAX			/* end marker */

diff --git a/src/libpfm4/lib/Makefile b/src/libpfm4/lib/Makefile
@@ -200,22 +200,34 @@ endif
 ifeq ($(CONFIG_PFMLIB_ARCH_ARM),y)
 
 ifeq ($(SYS),Linux)
-SRCS += pfmlib_arm_perf_event.c
+SRCS += pfmlib_arm_perf_event.c pfmlib_arm_armv8_thunderx2_unc_perf_event.c pfmlib_arm_armv8_kunpeng_unc_perf_event.c
 endif
 
 INCARCH = $(INC_ARM)
-SRCS   += pfmlib_arm.c pfmlib_arm_armv7_pmuv1.c pfmlib_arm_armv6.c pfmlib_arm_armv8.c pfmlib_arm_armv9.c pfmlib_tx2_unc_perf_event.c pfmlib_kunpeng_unc_perf_event.c
+SRCS   += pfmlib_arm.c \
+	  pfmlib_arm_armv7_pmuv1.c \
+	  pfmlib_arm_armv6.c \
+	  pfmlib_arm_armv8.c \
+	  pfmlib_arm_armv9.c \
+	  pfmlib_arm_armv8_thunderx2_unc.c \
+	  pfmlib_arm_armv8_kunpeng_unc.c
+
 CFLAGS += -DCONFIG_PFMLIB_ARCH_ARM
 endif
 
 ifeq ($(CONFIG_PFMLIB_ARCH_ARM64),y)
 
 ifeq ($(SYS),Linux)
-SRCS += pfmlib_arm_perf_event.c
+SRCS += pfmlib_arm_perf_event.c pfmlib_arm_armv8_thunderx2_unc_perf_event.c pfmlib_arm_armv8_kunpeng_unc_perf_event.c
 endif
 
 INCARCH = $(INC_ARM64)
-SRCS   += pfmlib_arm.c pfmlib_arm_armv8.c pfmlib_arm_armv9.c pfmlib_tx2_unc_perf_event.c pfmlib_kunpeng_unc_perf_event.c
+SRCS   += pfmlib_arm.c \
+	  pfmlib_arm_armv8.c \
+	  pfmlib_arm_armv9.c \
+	  pfmlib_arm_armv8_thunderx2_unc.c \
+	  pfmlib_arm_armv8_kunpeng_unc.c
+
 CFLAGS += -DCONFIG_PFMLIB_ARCH_ARM64
 endif
 
@@ -415,6 +427,7 @@ INC_ARM=pfmlib_arm_priv.h			\
 	events/arm_neoverse_n2_events.h		\
 	events/arm_neoverse_v1_events.h		\
 	events/arm_neoverse_v2_events.h		\
+	events/arm_neoverse_v3_events.h		\
 	events/arm_hisilicon_kunpeng_events.h \
 	events/arm_hisilicon_kunpeng_unc_events.h
 
@@ -429,6 +442,7 @@ INC_ARM64=pfmlib_arm_priv.h			\
 	events/arm_neoverse_n2_events.h		\
 	events/arm_neoverse_v1_events.h		\
 	events/arm_neoverse_v2_events.h		\
+	events/arm_neoverse_v3_events.h		\
 	events/arm_hisilicon_kunpeng_events.h \
 	events/arm_hisilicon_kunpeng_unc_events.h