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commit c89a379175c00a20bbc660ad9b444e8ecc16cd28
Author: Stephane Eranian <eranian@gmail.com>
Date:   Sat Sep 21 21:11:10 2024 -0700

    add ARM Cortex A76 core PMU support

    Adds ARM Cortex A76 core PMU support.
    Based on:
            https://github.com/ARM-software/data/blob/master/pmu/cortex-a76.json

    Signed-off-by: Stephane Eranian <eranian@gmail.com>

commit 6195cbb4686dbeeee7a237ab8a133ef6c2209476
Author: Stephane Eranian <eranian@gmail.com>
Date:   Sat Sep 21 20:50:17 2024 -0700

    fix detection of ARM Cortex A55

    Was using code not yet released.
    Bug introduced by:
    c40b6eb0640a ("add ARM Cortex A55 core PMU support")

    Signed-off-by: Stephane Eranian <eranian@gmail.com>

commit 1e8734203f74f0ec6974a860c0b18cb95cce1371
Author: Sachin Monga <smonga@linux.ibm.com>
Date:   Thu Aug 15 12:54:51 2024 -0400

    Update IBM Power10 core PMU support

    Added additional events for IBM Power 10 core PMU.

    Signed-off-by: Sachin Monga <smonga@linux.ibm.com>

commit c40b6eb0640a649b2c3fdf472c1d6499a8e819c0
Author: Stephane Eranian <eranian@gmail.com>
Date:   Sat Sep 21 19:47:08 2024 -0700

    add ARM Cortex A55 core PMU support

    Add support for ARM Cortex A55 core PMU events.
    Based on:
            https://github.com/ARM-software/data/blob/master/pmu/cortex-a55.json

    Signed-off-by: Stephane Eranian <eranian@gmail.com>

commit f91ea4f1a76fdd5886fd9b6fe8eaa6f585a5bac4
Author: Stephane Eranian <eranian@gmail.com>
Date:   Thu Sep 19 21:23:59 2024 -0700

    fix ARM thunderX2 and HiSilicon support to compile on non Linux

    The perf_events encoding routines were mixed with generic encodings
    and event tables. This patch cleans all of this to separate generic
    from Linux specific code.

commit 892c5fc89ed5fc0e4f0b4a4a290fac57613f23da
Author: Stephane Eranian <eranian@gmail.com>
Date:   Thu Sep 19 00:38:14 2024 -0700

    Add ARM Neoverse V3 core PMU support

    Based on:
       https://github.com/ARM-software/data/blob/master/pmu/neoverse-v3.json

    Signed-off-by: Stephane Eranian <eranian@gmail.com>

Note: Below are the commits grouped from top to bottom and discusses what was able to be tested and what was not.

 - Commit ID with last 6 of 16cd28, unable to test due to no access to a machine with ARM Cortex A76.
 - Commit ID with last 6 of 209476, unable to test update due to no access to a machine with ARM Cortex A55.
 - Commit ID with last 6 of ce1371, unable to test as stands, requesting access at Oregon for a machine with Power 10 and will update once testing is completed.
   Commit ID with last 6 of e819c0, unable to test update due to no access to a machine with ARM Cortex A55.
 - Commit ID's with last 6 of a5bac4 and 3f23da, unable to test updates due to no access to a machine with either ARM Neoverse V3, ARM thunderX2 and HiSilicon.
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Treece Burgess committed Sep 23, 2024
1 parent 3ad9b90 commit df29a50
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Showing 25 changed files with 3,481 additions and 329 deletions.
3 changes: 2 additions & 1 deletion src/libpfm4/README
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Expand Up @@ -78,12 +78,13 @@ The library supports many PMUs. The current version can handle:
ARMV7 Cortex A8
ARMV7 Cortex A9
ARMV7 Cortex A15
ARMV8 Cortex A57, A53, A72
ARMV8 Cortex A57, A53, A55, A72, A76
Applied Micro X-Gene
Qualcomm Krait
Fujitsu A64FX
Arm Neoverse V1
Arm Neoverse V2
Arm Neoverse V3
Huawei HiSilicon Kunpeng 920

- For SPARC
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16 changes: 11 additions & 5 deletions src/libpfm4/docs/Makefile
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Expand Up @@ -146,27 +146,33 @@ ARCH_MAN += libpfm_arm_xgene.3 \
libpfm_arm_ac7.3 \
libpfm_arm_ac57.3 \
libpfm_arm_ac53.3 \
libpfm_arm_ac55.3 \
libpfm_arm_ac72.3 \
libpfm_arm_ac76.3 \
libpfm_arm_ac15.3 \
libpfm_arm_ac8.3 \
libpfm_arm_ac9.3 \
libpfm_arm_qcom_krait.3 \
libpfm_arm_neoverse_n1.3 \
libpfm_arm_neoverse_n2.3 \
libpfm_arm_neoverse_v1.3 \
libpfm_arm_neoverse_v2.3
libpfm_arm_neoverse_v1.3 \
libpfm_arm_neoverse_v2.3 \
libpfm_arm_neoverse_v3.3
endif

ifeq ($(CONFIG_PFMLIB_ARCH_ARM64),y)
ARCH_MAN += libpfm_arm_xgene.3 \
libpfm_arm_ac57.3 \
libpfm_arm_ac53.3 \
libpfm_arm_ac55.3 \
libpfm_arm_ac72.3 \
libpfm_arm_ac76.3 \
libpfm_arm_a64fx.3 \
libpfm_arm_neoverse_n1.3 \
libpfm_arm_neoverse_n1.3 \
libpfm_arm_neoverse_n2.3 \
libpfm_arm_neoverse_v1.3 \
libpfm_arm_neoverse_v2.3
libpfm_arm_neoverse_v1.3 \
libpfm_arm_neoverse_v2.3 \
libpfm_arm_neoverse_v3.3
endif

ifeq ($(CONFIG_PFMLIB_ARCH_MIPS),y)
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36 changes: 36 additions & 0 deletions src/libpfm4/docs/man3/libpfm_arm_ac55.3
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@@ -0,0 +1,36 @@
.TH LIBPFM 3 "September, 2024" "" "Linux Programmer's Manual"
.SH NAME
libpfm_arm_ac55 - support for ARM Cortex A55 PMU
.SH SYNOPSIS
.nf
.B #include <perfmon/pfmlib.h>
.sp
.B PMU name: arm_ac55
.B PMU desc: ARM Cortex A55
.sp
.SH DESCRIPTION
The library supports the ARM Cortex A55 core PMU.

This PMU supports 6 counters and privilege levels filtering.
It can operate in both 32 and 64 bit modes.

.SH MODIFIERS
The following modifiers are supported on ARM Cortex A55:
.TP
.B u
Measure at the user level. This corresponds to \fBPFM_PLM3\fR.
This is a boolean modifier.
.TP
.B k
Measure at the kernel level. This corresponds to \fBPFM_PLM0\fR.
This is a boolean modifier.
.TP
.B hv
Measure at the hypervisor level. This corresponds to \fBPFM_PLMH\fR.
This is a boolean modifier.

.SH AUTHORS
.nf
Stephane Eranian <eranian@gmail.com>
.if
.PP
36 changes: 36 additions & 0 deletions src/libpfm4/docs/man3/libpfm_arm_ac76.3
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@@ -0,0 +1,36 @@
.TH LIBPFM 3 "September, 2024" "" "Linux Programmer's Manual"
.SH NAME
libpfm_arm_ac76 - support for Arm Cortex A76 PMU
.SH SYNOPSIS
.nf
.B #include <perfmon/pfmlib.h>
.sp
.B PMU name: arm_ac76
.B PMU desc: ARM Cortex A76
.sp
.SH DESCRIPTION
The library supports the ARM Cortex A76 core PMU.

This PMU supports 6 counters and privilege levels filtering.
It can operate in both 32 and 64 bit modes.

.SH MODIFIERS
The following modifiers are supported on ARM Cortex A76:
.TP
.B u
Measure at the user level. This corresponds to \fBPFM_PLM3\fR.
This is a boolean modifier.
.TP
.B k
Measure at the kernel level. This corresponds to \fBPFM_PLM0\fR.
This is a boolean modifier.
.TP
.B hv
Measure at the hypervisor level. This corresponds to \fBPFM_PLMH\fR.
This is a boolean modifier.

.SH AUTHORS
.nf
Stephane Eranian <eranian@gmail.com>
.if
.PP
36 changes: 36 additions & 0 deletions src/libpfm4/docs/man3/libpfm_arm_neoverse_v3.3
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@@ -0,0 +1,36 @@
.TH LIBPFM 3 "September, 2024" "" "Linux Programmer's Manual"
.SH NAME
libpfm_arm_neoverse_v3 - support for Arm Neoverse V3 core PMU
.SH SYNOPSIS
.nf
.B #include <perfmon/pfmlib.h>
.sp
.B PMU name: arm_v3
.B PMU desc: Arm Neoverse V3
.sp
.SH DESCRIPTION
The library supports the Arm Neoverse V3 core PMU.

This PMU supports 6 counters and privilege levels filtering.
It can operate in both 32 and 64 bit modes.

.SH MODIFIERS
The following modifiers are supported on Arm Neoverse V3:
.TP
.B u
Measure at the user level. This corresponds to \fBPFM_PLM3\fR.
This is a boolean modifier.
.TP
.B k
Measure at the kernel level. This corresponds to \fBPFM_PLM0\fR.
This is a boolean modifier.
.TP
.B hv
Measure at the hypervisor level. This corresponds to \fBPFM_PLMH\fR.
This is a boolean modifier.

.SH AUTHORS
.nf
Stephane Eranian <eranian@gmail.com>
.if
.PP
3 changes: 3 additions & 0 deletions src/libpfm4/include/perfmon/pfmlib.h
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Original file line number Diff line number Diff line change
Expand Up @@ -816,6 +816,9 @@ typedef enum {
PFM_PMU_AMD64_FAM1AH_ZEN5_L3, /* AMD64 Fam1Ah Zen5 L3 */

PFM_PMU_ARM_CORTEX_A72, /* ARM Cortex A72 (ARMv8) */
PFM_PMU_ARM_V3, /* Arm Neoverse V3 (ARMv9) */
PFM_PMU_ARM_CORTEX_A55, /* ARM Cortex A55 (ARMv8) */
PFM_PMU_ARM_CORTEX_A76, /* ARM Cortex A76 (ARMv8) */
/* MUST ADD NEW PMU MODELS HERE */

PFM_PMU_MAX /* end marker */
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22 changes: 18 additions & 4 deletions src/libpfm4/lib/Makefile
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Expand Up @@ -200,22 +200,34 @@ endif
ifeq ($(CONFIG_PFMLIB_ARCH_ARM),y)

ifeq ($(SYS),Linux)
SRCS += pfmlib_arm_perf_event.c
SRCS += pfmlib_arm_perf_event.c pfmlib_arm_armv8_thunderx2_unc_perf_event.c pfmlib_arm_armv8_kunpeng_unc_perf_event.c
endif

INCARCH = $(INC_ARM)
SRCS += pfmlib_arm.c pfmlib_arm_armv7_pmuv1.c pfmlib_arm_armv6.c pfmlib_arm_armv8.c pfmlib_arm_armv9.c pfmlib_tx2_unc_perf_event.c pfmlib_kunpeng_unc_perf_event.c
SRCS += pfmlib_arm.c \
pfmlib_arm_armv7_pmuv1.c \
pfmlib_arm_armv6.c \
pfmlib_arm_armv8.c \
pfmlib_arm_armv9.c \
pfmlib_arm_armv8_thunderx2_unc.c \
pfmlib_arm_armv8_kunpeng_unc.c

CFLAGS += -DCONFIG_PFMLIB_ARCH_ARM
endif

ifeq ($(CONFIG_PFMLIB_ARCH_ARM64),y)

ifeq ($(SYS),Linux)
SRCS += pfmlib_arm_perf_event.c
SRCS += pfmlib_arm_perf_event.c pfmlib_arm_armv8_thunderx2_unc_perf_event.c pfmlib_arm_armv8_kunpeng_unc_perf_event.c
endif

INCARCH = $(INC_ARM64)
SRCS += pfmlib_arm.c pfmlib_arm_armv8.c pfmlib_arm_armv9.c pfmlib_tx2_unc_perf_event.c pfmlib_kunpeng_unc_perf_event.c
SRCS += pfmlib_arm.c \
pfmlib_arm_armv8.c \
pfmlib_arm_armv9.c \
pfmlib_arm_armv8_thunderx2_unc.c \
pfmlib_arm_armv8_kunpeng_unc.c

CFLAGS += -DCONFIG_PFMLIB_ARCH_ARM64
endif

Expand Down Expand Up @@ -415,6 +427,7 @@ INC_ARM=pfmlib_arm_priv.h \
events/arm_neoverse_n2_events.h \
events/arm_neoverse_v1_events.h \
events/arm_neoverse_v2_events.h \
events/arm_neoverse_v3_events.h \
events/arm_hisilicon_kunpeng_events.h \
events/arm_hisilicon_kunpeng_unc_events.h

Expand All @@ -429,6 +442,7 @@ INC_ARM64=pfmlib_arm_priv.h \
events/arm_neoverse_n2_events.h \
events/arm_neoverse_v1_events.h \
events/arm_neoverse_v2_events.h \
events/arm_neoverse_v3_events.h \
events/arm_hisilicon_kunpeng_events.h \
events/arm_hisilicon_kunpeng_unc_events.h

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