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Fix precommit
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Signed-off-by: Tiotto, Ettore <ettore.tiotto@intel.com>
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etiotto committed May 22, 2024
1 parent 3c80488 commit 5833762
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Showing 2 changed files with 4 additions and 4 deletions.
6 changes: 3 additions & 3 deletions test/TritonIntelGPU/prefetch-to-llvm.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -10,9 +10,9 @@
#dot1 = #triton_gpu.dot_op<{opIdx = 1, parent = #dpas, kWidth = 2}>
module attributes {"triton_gpu.num-warps" = 8 : i32, "triton_gpu.threads-per-warp" = 16 : i32} {
tt.func public @matmul_with_prefetch(%arg0: !tt.ptr<f16>, %arg1: !tt.ptr<f16>, %arg2: tensor<32x32x!tt.ptr<f32>, #blocked>, %arg3: i64, %arg4: i64, %arg5: i64, %arg6: i64, %arg7: i64) {
// CHECK-LABEL: @matmul_with_prefetch
// CHECK-LABEL: @matmul_with_prefetch
// CHECK-COUNT-2: llvm.call @llvm.genx.GenISA.LSC2DBlockPrefetch.isVoid{{.*}} -> ()
// CHECK-COUNT-1: llvm.call @llvm.genx.GenISA.LSC2DBlockRead.v8i16{{.*}} -> vector<8xi16>
// CHECK-COUNT-1: llvm.call @llvm.genx.GenISA.LSC2DBlockRead.v8i16{{.*}} -> vector<8xi16>
// CHECK-COUNT-1: llvm.call @llvm.genx.GenISA.LSC2DBlockRead.v8i32{{.*}} -> vector<8xi32>
// CHECK-COUNT-1: llvm.call @_Z38intel_sub_group_f16_f16_matrix_mad_k16Dv8_sDv8_iDv8_f({{.*}}) {passthrough = ["convergent"]} : (vector<8xi16>, vector<8xi32>, vector<8xf32>) -> vector<8xf32>
%cst = arith.constant dense<0.000000e+00> : tensor<32x32xf32, #dpas>
Expand All @@ -28,4 +28,4 @@ module attributes {"triton_gpu.num-warps" = 8 : i32, "triton_gpu.threads-per-war
%12 = triton_gpu.convert_layout %11 {allocation.offset = 0 : i32} : tensor<32x32xf32, #dpas> -> tensor<32x32xf32, #blocked>
tt.return
}
}
}
Original file line number Diff line number Diff line change
Expand Up @@ -186,7 +186,7 @@ struct PrefetchOpConversion
if (isTensorPointerType(ptr.getType()))
return rewriteTensorPointerPrefetch(op, adaptor, rewriter);

assert(false && "Unexpected prefetch operation on 'regular' ptr");
llvm_unreachable("Unexpected prefetch operation on 'regular' ptr");
return failure();
}

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