fix pitch restriction check + remove commented code

intel · Sep 26, 2024 · c09e10e · c09e10e
1 parent 8a4cab2
commit c09e10e
Showing 1 changed file with 2 additions and 3 deletions.
diff --git a/third_party/intel/lib/TritonIntelGPUTransforms/MaterializeBlockPointer.cpp b/third_party/intel/lib/TritonIntelGPUTransforms/MaterializeBlockPointer.cpp
@@ -71,9 +71,7 @@ struct TritonIntelGPUMaterializeBlockPointerPass
       }
       ArrayRef<int32_t> order = makeTensorPtrOp.getOrder();
 
-      // unsigned fastChangeDim = order[0];
       if (fastChangeDim >= (rank - 2)) {
-
         // HW 2D block read instruction only supports contiguous access.
         Value fastChangeStride = strides[fastChangeDim];
         LLVM_DEBUG({
@@ -89,7 +87,8 @@ struct TritonIntelGPUMaterializeBlockPointerPass
         Value pitch =
             strides[(fastChangeDim == rank - 1) ? rank - 2 : rank - 1];
         LDBG("Pitch: " << pitch);
-        if (!ttgi::isDivisible(pitch, 64 / tensorType.getElementTypeBitWidth()))
+        if (!ttgi::isDivisible(pitch,
+                               128 / tensorType.getElementTypeBitWidth()))
           return;
 
         loadOp->setAttr(ttgi::TritonIntelGPUDialect::getBlockIOAttrName(),