diff --git a/media_driver/agnostic/common/hw/mhw_mmio.h b/media_driver/agnostic/common/hw/mhw_mmio.h index 21320cae789..6da88ca0853 100644 --- a/media_driver/agnostic/common/hw/mhw_mmio.h +++ b/media_driver/agnostic/common/hw/mhw_mmio.h @@ -59,6 +59,10 @@ typedef struct _MHW_MI_MMIOREGISTERS uint32_t generalPurposeRegister0HiOffset; uint32_t generalPurposeRegister4LoOffset; uint32_t generalPurposeRegister4HiOffset; + uint32_t generalPurposeRegister11LoOffset; //!< __OCA_BUFFER_ADDR_LOW_MMIO + uint32_t generalPurposeRegister11HiOffset; //!< __OCA_BUFFER_ADDR_HIGH_MMIO + uint32_t generalPurposeRegister12LoOffset; //!< __OCA_BUFFER_IND_STATE_SECTION_OFFSET_MMIO + uint32_t generalPurposeRegister12HiOffset; //!< __OCA_BUFFER_BB_SECTION_OFFSET_MMIO } MHW_MI_MMIOREGISTERS, *PMHW_MI_MMIOREGISTERS; @@ -107,6 +111,10 @@ struct MmioRegistersMfx uint32_t generalPurposeRegister0HiOffset = 0; uint32_t generalPurposeRegister4LoOffset = 0; uint32_t generalPurposeRegister4HiOffset = 0; + uint32_t generalPurposeRegister11LoOffset = 0; //!< __OCA_BUFFER_ADDR_LOW_MMIO + uint32_t generalPurposeRegister11HiOffset = 0; //!< __OCA_BUFFER_ADDR_HIGH_MMIO + uint32_t generalPurposeRegister12LoOffset = 0; //!< __OCA_BUFFER_IND_STATE_SECTION_OFFSET_MMIO + uint32_t generalPurposeRegister12HiOffset = 0; //!< __OCA_BUFFER_BB_SECTION_OFFSET_MMIO uint32_t mfcImageStatusMaskRegOffset = 0; uint32_t mfcImageStatusCtrlRegOffset = 0; uint32_t mfcAvcNumSlicesRegOffset = 0; diff --git a/media_driver/agnostic/common/hw/mhw_render.h b/media_driver/agnostic/common/hw/mhw_render.h index d268990c47d..fc5d244c88a 100644 --- a/media_driver/agnostic/common/hw/mhw_render.h +++ b/media_driver/agnostic/common/hw/mhw_render.h @@ -578,6 +578,14 @@ class MhwRenderInterface //! void SetOsInterface(PMOS_INTERFACE osInterface) { m_osInterface = osInterface;} + //! + //! \brief Get mmio registers address + //! \details Get mmio registers address + //! \return [out] PMHW_MI_MMIOREGISTERS* + //! mmio registers got. + //! + virtual PMHW_MI_MMIOREGISTERS GetMmioRegisters() = 0; + protected: //! //! \brief Initializes the Render interface diff --git a/media_driver/agnostic/common/os/media_srcs.cmake b/media_driver/agnostic/common/os/media_srcs.cmake index dbd4c804c79..411d52039ed 100644 --- a/media_driver/agnostic/common/os/media_srcs.cmake +++ b/media_driver/agnostic/common/os/media_srcs.cmake @@ -49,6 +49,7 @@ set(TMP_HEADERS_ ${CMAKE_CURRENT_LIST_DIR}/mos_gpucontextmgr.h ${CMAKE_CURRENT_LIST_DIR}/mos_cmdbufmgr.h ${CMAKE_CURRENT_LIST_DIR}/mos_commandbuffer.h + ${CMAKE_CURRENT_LIST_DIR}/mos_oca_interface.h ) set(SOURCES_ diff --git a/media_driver/agnostic/common/os/mos_defs.h b/media_driver/agnostic/common/os/mos_defs.h index fc7076d3f79..cc3960c68e8 100644 --- a/media_driver/agnostic/common/os/mos_defs.h +++ b/media_driver/agnostic/common/os/mos_defs.h @@ -333,7 +333,8 @@ typedef enum _MOS_STATUS MOS_STATUS_CLIENT_AR_NO_SPACE = 28, MOS_STATUS_HUC_KERNEL_FAILED = 29, MOS_STATUS_NOT_ENOUGH_BUFFER = 30, - MOS_STATUS_UNKNOWN = 31 + MOS_STATUS_UNINITIALIZED = 31, + MOS_STATUS_UNKNOWN = 32 } MOS_STATUS; //! diff --git a/media_driver/agnostic/common/os/mos_oca_interface.h b/media_driver/agnostic/common/os/mos_oca_interface.h new file mode 100644 index 00000000000..412ca7bdd27 --- /dev/null +++ b/media_driver/agnostic/common/os/mos_oca_interface.h @@ -0,0 +1,211 @@ +/* +* Copyright (c) 2009-2019, Intel Corporation +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +*/ +//! +//! \file mos_oca_interface.h +//! \brief Common interface and structure for OCA +//! + +#ifndef __MOS_OCA_INTERFACE_H__ +#define __MOS_OCA_INTERFACE_H__ + +typedef uint64_t MOS_OCA_BUFFER_HANDLE; +#define OCA_HEAP_INVALID_OFFSET ((uint32_t)-1) + +typedef struct _MOS_OCA_LOG_HEADER +{ + uint32_t m_Type; //!< Oca log type. Refer to MOS_OCA_LOG_TYPE. + uint32_t m_HeaderSize; //!< The size for extented message header. + uint32_t m_DataSize; //!< The size of data block without message header. +}MOS_OCA_LOG_HEADER, *PMOS_OCA_LOG_HEADER; + +class MosOcaInterface +{ +public: + //! + //! \brief Destructor + //! + virtual ~MosOcaInterface() {} + + //! + //! \brief Get the idle oca buffer, which is neither used by hw nor locked, and lock it for edit. + //! \param [in] pMosContext + //! pointer to MOS_INTERFACE + //! \param [in] CurrentGpuContextHandle + //! Gpu context handle + //! \return MOS_OCA_BUFFER_HANDLE + //! return the handle for oca buffer + //! + virtual MOS_OCA_BUFFER_HANDLE LockOcaBufAvailable(PMOS_CONTEXT pMosContext, uint32_t CurrentGpuContextHandle) + { + return 0; + } + + //! + //! \brief Unlock the oca buffer when edit complete. + //! \param [in] hOcaBuf + //! Oca buffer handle. + //! \return MOS_STATUS + //! Return MOS_STATUS_SUCCESS if successful, otherwise failed + //! + virtual MOS_STATUS UnlockOcaBuf(MOS_OCA_BUFFER_HANDLE hOcaBuf) + { + return MOS_STATUS_UNIMPLEMENTED; + } + + //! + //! \brief Oca operation which should be called at the beginning of 1st level batch buffer start. + //! \param [out] gpuVaOcaBuffer + //! The gfx virtual address of oca buffer, which should be set to GPR11 by LRI at the + //! beginning of 1st level batch buffer no matter return value is MOS_STATUS_SUCCESS or not. + //! \param [in] hOcaBuf + //! Oca buffer handle. + //! \param [in] pMosContext + //! Pointer to MOS_CONTEXT. + //! \param [in] pMosResource + //! Pointer to the MOS_RESOURCE. + //! \param [in] offsetOf1stLevelBB + //! Offset for current BB in pMosResource. + //! \param [in] bUseSizeOfResource + //! If true, use size of pMosResource for batch buffer, else use sizeOf1stLevelBB. + //! \param [in] sizeOf1stLevelBB + //! Size of BB. Ignore if bUseSizeOfResource == true. + //! \return MOS_STATUS + //! Return MOS_STATUS_SUCCESS if successful, otherwise failed + //! + virtual MOS_STATUS On1stLevelBBStart(uint64_t &gpuVaOcaBuffer, MOS_OCA_BUFFER_HANDLE hOcaBuf, PMOS_CONTEXT pMosContext, void *pMosResource, + uint32_t offsetOf1stLevelBB, bool bUseSizeOfResource, uint32_t sizeOf1stLevelBB) + { + // The GPR11 need to be reset to 0 to disable UMD_OCA for current workload. + gpuVaOcaBuffer = 0; + return MOS_STATUS_UNIMPLEMENTED; + } + + //! + //! \brief Oca operation which should be called before adding batch buffer end command for 1st + //! level batch buffer. + //! \param [in] hOcaBuf + //! Oca buffer handle. + //! \return MOS_STATUS + //! Return MOS_STATUS_SUCCESS if successful, otherwise failed + //! + virtual MOS_STATUS On1stLevelBBEnd(MOS_OCA_BUFFER_HANDLE hOcaBuf) + { + return MOS_STATUS_UNIMPLEMENTED; + } + + //! + //! \brief Oca operation which should be called before sending start sub level batch buffer command. + //! \param [in] hOcaBuf + //! Oca buffer handle. + //! \param [in] pMosContext + //! Pointer to MOS_CONTEXT. + //! \param [in] pMosResource + //! Pointer to the MOS_RESOURCE. + //! \param [in] offsetOfSubLevelBB + //! Offset for current BB in pMosResource. + //! \param [in] bUseSizeOfResource + //! If true, use size of pMosResource for batch buffer, else use sizeOfIndirectState. + //! \param [in] sizeOfSubLevelBB + //! Size of BB. Ignore if bUseSizeOfResource == true. + //! \return MOS_STATUS + //! Return MOS_STATUS_SUCCESS if successful, otherwise failed + //! + MOS_STATUS OnSubLevelBBStart(MOS_OCA_BUFFER_HANDLE hOcaBuf, PMOS_CONTEXT pMosContext, void *pMosResource, uint32_t offsetOfSubLevelBB, bool bUseSizeOfResource, uint32_t sizeOfSubLevelBB) + { + return MOS_STATUS_UNIMPLEMENTED; + } + + //! + //! \brief Oca operation which should be called when indirect states being added. + //! \param [in] hOcaBuf + //! Oca buffer handle. + //! \param [in] pMosContext + //! Pointer to MOS_CONTEXT. + //! \param [in] pMosResource + //! Pointer to the MOS_RESOURCE. + //! \param [in] offsetOfIndirectState + //! Offset for current state in pMosResource. + //! \param [in] bUseSizeOfResource + //! If true, use size of pMosResource for indirect state, else use sizeOfIndirectState. + //! \param [in] sizeOfIndirectState + //! Size of indirect state. Ignore if bUseSizeOfResource == true. + //! \return MOS_STATUS + //! Return MOS_STATUS_SUCCESS if successful, otherwise failed + //! + virtual MOS_STATUS OnIndirectState(MOS_OCA_BUFFER_HANDLE hOcaBuf, PMOS_CONTEXT pMosContext, void *pMosResource, uint32_t offsetOfIndirectState, bool bUseSizeOfResource, uint32_t sizeOfIndirectState) + { + return MOS_STATUS_UNIMPLEMENTED; + } + + //! + //! \brief Oca operation which should be called before adding dispatch states, + //! e.g. VEB_DI_IECP_STATE and MEDIA_OBJECT_WALKER. + //! \param [out] offsetInIndirectStateHeap + //! The start offset of current dispatch in indirect state heap, which should be set to low 32 bits + //! of GPR12 by LRI before dispatch commands being added. + //! OCA_HEAP_INVALID_OFFSET means no need to configure GPR12, otherwise the register need be configured + //! no matter return value being MOS_STATUS_SUCCESS or not. + //! \param [in] hOcaBuf + //! Oca buffer handle. + //! \return MOS_STATUS + //! Return MOS_STATUS_SUCCESS if successful, otherwise failed + //! + virtual MOS_STATUS OnDispatch(uint32_t &offsetInIndirectStateHeap, MOS_OCA_BUFFER_HANDLE hOcaBuf) + { + offsetInIndirectStateHeap = OCA_HEAP_INVALID_OFFSET; + return MOS_STATUS_UNIMPLEMENTED; + } + + //! + //! \brief Add string to oca log section + //! \param [in] hOcaBuf + //! Oca buffer handle. + //! \param [in] str + //! string to be added. + //! \param [in] maxCount + //! size of the buffer pointed by str. + //! \return MOS_STATUS + //! Return MOS_STATUS_SUCCESS if successful, otherwise failed + //! + virtual MOS_STATUS TraceMessage(MOS_OCA_BUFFER_HANDLE hOcaBuf, const char *str, uint32_t maxCount) + { + return MOS_STATUS_UNIMPLEMENTED; + } + + //! + //! \brief Add data block to oca log section. + //! \param [in] hOcaBuf + //! Oca buffer handle. + //! \param [in] pHeader + //! Log header. It can be extended by user. The acutal size of header is pHeader->m_HeaderSize. + //! \param [in] pData + //! Data block without log header. The acutal size of data block is pHeader->m_DataSize. + //! \return MOS_STATUS + //! Return MOS_STATUS_SUCCESS if successful, otherwise failed + //! + virtual MOS_STATUS DumpDataBlock(MOS_OCA_BUFFER_HANDLE hOcaBuf, PMOS_OCA_LOG_HEADER pHeader, void *pData) + { + return MOS_STATUS_UNIMPLEMENTED; + } +}; + +#endif // #ifndef __MOS_OCA_INTERFACE_H__ diff --git a/media_driver/agnostic/common/os/mos_os.h b/media_driver/agnostic/common/os/mos_os.h index 3be0939be62..ed27d47f01d 100644 --- a/media_driver/agnostic/common/os/mos_os.h +++ b/media_driver/agnostic/common/os/mos_os.h @@ -45,6 +45,8 @@ #include "mos_os_specific.h" #include "mos_os_virtualengine_specific.h" +#include "mos_oca_interface.h" + #define MOS_NAL_UNIT_LENGTH 4 #define MOS_NAL_UNIT_STARTCODE_LENGTH 3 #define MOS_MAX_PATH_LENGTH 256 @@ -238,6 +240,7 @@ typedef struct _MOS_COMMAND_BUFFER MOS_VDBOX_NODE_IND iVdboxNodeIndex; //!< Which VDBOX buffer is binded to MOS_COMMAND_BUFFER_ATTRIBUTES Attributes; //!< Attributes for the command buffer to be provided to KMD at submission + MOS_OCA_BUFFER_HANDLE hOcaBuf; //!< Oca buffer handle for current command } MOS_COMMAND_BUFFER; //! diff --git a/media_driver/agnostic/common/os/mos_os_trace_event.h b/media_driver/agnostic/common/os/mos_os_trace_event.h index 4dc8149d42f..deb9b64cb9e 100644 --- a/media_driver/agnostic/common/os/mos_os_trace_event.h +++ b/media_driver/agnostic/common/os/mos_os_trace_event.h @@ -102,7 +102,8 @@ typedef enum _MEDIA_EVENT EVENT_DDE_CB_REPORT_ENCRYPTION_STATUS, EVENT_DDE_CB_REPORT_LINK_STATUS, EVENT_DDE_CB_SEND_DATA, - EVENT_DDE_MESSAGE //! event for debug message + EVENT_DDE_MESSAGE, //! event for debug message + EVENT_OCA_LAST_ERROR //! event for last OCA error. } MEDIA_EVENT; typedef enum _MEDIA_EVENT_TYPE diff --git a/media_driver/agnostic/common/os/mos_util_user_feature_keys.h b/media_driver/agnostic/common/os/mos_util_user_feature_keys.h index 815182f4714..6fb434fc418 100644 --- a/media_driver/agnostic/common/os/mos_util_user_feature_keys.h +++ b/media_driver/agnostic/common/os/mos_util_user_feature_keys.h @@ -274,4 +274,7 @@ //User feature key for enable simulating random memory allocation failure #define __MEDIA_USER_FEATURE_VALUE_SIMULATE_RANDOM_ALLOC_MEMORY_FAIL "Simulate Random Alloc Memory Fail" +//User feature key for enable/disable UMD_OCA +#define __MEDIA_USER_FEATURE_VALUE_ENABLE_UMD_OCA "Enable UMD_OCA" + #endif // __MOS_UTIL_USER_FEATURE_KEYS_H__ diff --git a/media_driver/agnostic/common/os/mos_utilities.c b/media_driver/agnostic/common/os/mos_utilities.c index 039f56c2bd2..f4b938bf7d8 100644 --- a/media_driver/agnostic/common/os/mos_utilities.c +++ b/media_driver/agnostic/common/os/mos_utilities.c @@ -3465,7 +3465,7 @@ static MOS_USER_FEATURE_VALUE MOSUserFeatureDescFields[__MOS_USER_FEATURE_KEY_MA MOS_USER_FEATURE_VALUE_TYPE_UINT32, "0", "Enable MOS to simualte random memory allocate fail. "), - MOS_DECLARE_UF_KEY_DBGONLY(__MEDIA_USER_FEATURE_VALUE_EXTERNAL_COPY_SYNC_ID, + MOS_DECLARE_UF_KEY_DBGONLY(__MEDIA_USER_FEATURE_VALUE_EXTERNAL_COPY_SYNC_ID, "External Copy Sync", __MEDIA_USER_FEATURE_SUBKEY_INTERNAL, __MEDIA_USER_FEATURE_SUBKEY_INTERNAL, @@ -3474,6 +3474,15 @@ static MOS_USER_FEATURE_VALUE MOSUserFeatureDescFields[__MOS_USER_FEATURE_KEY_MA MOS_USER_FEATURE_VALUE_TYPE_UINT32, "0", "Enable GPU polling based sync for external raw surface copy."), + MOS_DECLARE_UF_KEY(__MEDIA_USER_FEATURE_VALUE_ENABLE_UMD_OCA_ID, + __MEDIA_USER_FEATURE_VALUE_ENABLE_UMD_OCA, + __MEDIA_USER_FEATURE_SUBKEY_INTERNAL, + __MEDIA_USER_FEATURE_SUBKEY_REPORT, + "MOS", + MOS_USER_FEATURE_TYPE_USER, + MOS_USER_FEATURE_VALUE_TYPE_UINT32, + "0", + "Enable UMD_OCA in media driver. This key is not valid on Linux."), }; #define MOS_NUM_USER_FEATURE_VALUES (sizeof(MOSUserFeatureDescFields) / sizeof(MOSUserFeatureDescFields[0])) diff --git a/media_driver/agnostic/common/os/mos_utilities.h b/media_driver/agnostic/common/os/mos_utilities.h index fffc0758043..18e60149d41 100644 --- a/media_driver/agnostic/common/os/mos_utilities.h +++ b/media_driver/agnostic/common/os/mos_utilities.h @@ -556,6 +556,7 @@ typedef enum _MOS_USER_FEATURE_VALUE_ID __MEDIA_USER_FEATURE_VALUE_SUPER_RESOLUTION_MODE_ID, __MEDIA_USER_FEATURE_VALUE_SIMULATE_RANDOM_ALLOC_MEMORY_FAIL_ID, __MEDIA_USER_FEATURE_VALUE_EXTERNAL_COPY_SYNC_ID, + __MEDIA_USER_FEATURE_VALUE_ENABLE_UMD_OCA_ID, __MOS_USER_FEATURE_KEY_MAX_ID, } MOS_USER_FEATURE_VALUE_ID; diff --git a/media_driver/agnostic/common/renderhal/media_srcs.cmake b/media_driver/agnostic/common/renderhal/media_srcs.cmake index 6d7af2ccafd..f748a5feace 100644 --- a/media_driver/agnostic/common/renderhal/media_srcs.cmake +++ b/media_driver/agnostic/common/renderhal/media_srcs.cmake @@ -22,6 +22,7 @@ set(TMP_SOURCES_ ${CMAKE_CURRENT_LIST_DIR}/renderhal.cpp ${CMAKE_CURRENT_LIST_DIR}/renderhal_dsh.cpp ${CMAKE_CURRENT_LIST_DIR}/renderhal_common.cpp + ${CMAKE_CURRENT_LIST_DIR}/renderhal_oca_support.cpp ) set(TMP_HEADERS_ @@ -29,6 +30,7 @@ set(TMP_HEADERS_ ${CMAKE_CURRENT_LIST_DIR}/renderhal_dsh.h ${CMAKE_CURRENT_LIST_DIR}/renderhal_platform_interface.h ${CMAKE_CURRENT_LIST_DIR}/vphal_renderhal_common.h + ${CMAKE_CURRENT_LIST_DIR}/renderhal_oca_support.h ) diff --git a/media_driver/agnostic/common/renderhal/renderhal.cpp b/media_driver/agnostic/common/renderhal/renderhal.cpp index 5b3035477d2..72665ac9c03 100644 --- a/media_driver/agnostic/common/renderhal/renderhal.cpp +++ b/media_driver/agnostic/common/renderhal/renderhal.cpp @@ -2031,6 +2031,7 @@ int32_t RenderHal_LoadKernel( iSize = MOS_ALIGN_CEIL(iKernelSize, pRenderHal->StateHeapSettings.iKernelBlockSize); // Update heap + pStateHeap->iKernelUsedForDump = pStateHeap->iKernelUsed + iKernelSize; pStateHeap->iKernelUsed += iSize; // Load kernel @@ -2329,6 +2330,7 @@ void RenderHal_ResetKernels( pStateHeap->dwAccessCounter = 0; pStateHeap->iKernelSize = pRenderHal->StateHeapSettings.iKernelHeapSize; pStateHeap->iKernelUsed = 0; + pStateHeap->iKernelUsedForDump = 0; finish: return; @@ -4312,6 +4314,10 @@ MOS_STATUS RenderHal_SendCurbeLoad( MHW_CURBE_LOAD_PARAMS CurbeLoadParams; PRENDERHAL_STATE_HEAP pStateHeap; MOS_STATUS eStatus = MOS_STATUS_SUCCESS; + PMOS_INTERFACE pOsInterface = nullptr; + MOS_CONTEXT *pOsContext = nullptr; + MOS_OCA_BUFFER_HANDLE hOcaBuf = 0; + RenderhalOcaSupport *pRenderhalOcaSupport = nullptr; //----------------------------------------- MHW_RENDERHAL_CHK_NULL(pRenderHal); @@ -4319,10 +4325,16 @@ MOS_STATUS RenderHal_SendCurbeLoad( MHW_RENDERHAL_CHK_NULL(pRenderHal->pStateHeap); MHW_RENDERHAL_CHK_NULL(pRenderHal->pMhwRenderInterface); MHW_RENDERHAL_CHK_NULL(pRenderHal->pStateHeap->pCurMediaState); + MHW_RENDERHAL_CHK_NULL(pRenderHal->pOsInterface); + MHW_RENDERHAL_CHK_NULL(pRenderHal->pOsInterface->pOsContext); + MHW_RENDERHAL_CHK_NULL(pRenderHal->pfnGetOcaSupport); //----------------------------------------- - eStatus = MOS_STATUS_SUCCESS; - pStateHeap = pRenderHal->pStateHeap; + eStatus = MOS_STATUS_SUCCESS; + pStateHeap = pRenderHal->pStateHeap; + pOsInterface = pRenderHal->pOsInterface; + pOsContext = pOsInterface->pOsContext; + pRenderhalOcaSupport = &pRenderHal->pfnGetOcaSupport(); // CURBE size is in bytes if (pStateHeap->pCurMediaState->iCurbeOffset != 0) @@ -4333,6 +4345,9 @@ MOS_STATUS RenderHal_SendCurbeLoad( CurbeLoadParams.dwCURBEDataStartAddress = pStateHeap->pCurMediaState->dwOffset + pStateHeap->dwOffsetCurbe; MHW_RENDERHAL_CHK_STATUS(pRenderHal->pMhwRenderInterface->AddMediaCurbeLoadCmd(pCmdBuffer, &CurbeLoadParams)); + + pRenderhalOcaSupport->OnIndirectState(*pCmdBuffer, *pOsContext,pRenderHal->StateBaseAddressParams.presDynamicState, + CurbeLoadParams.dwCURBEDataStartAddress, false, CurbeLoadParams.dwCURBETotalDataLength); } finish: @@ -4346,6 +4361,10 @@ MOS_STATUS RenderHal_SendMediaIdLoad( MHW_ID_LOAD_PARAMS IdLoadParams; PRENDERHAL_STATE_HEAP pStateHeap; MOS_STATUS eStatus = MOS_STATUS_SUCCESS; + PMOS_INTERFACE pOsInterface = nullptr; + MOS_CONTEXT *pOsContext = nullptr; + MOS_OCA_BUFFER_HANDLE hOcaBuf = 0; + RenderhalOcaSupport *pRenderhalOcaSupport = nullptr; //----------------------------------------- MHW_RENDERHAL_CHK_NULL(pRenderHal); @@ -4353,10 +4372,16 @@ MOS_STATUS RenderHal_SendMediaIdLoad( MHW_RENDERHAL_CHK_NULL(pRenderHal->pStateHeap); MHW_RENDERHAL_CHK_NULL(pRenderHal->pStateHeap->pCurMediaState); MHW_RENDERHAL_CHK_NULL(pRenderHal->pMhwRenderInterface); + MHW_RENDERHAL_CHK_NULL(pRenderHal->pOsInterface); + MHW_RENDERHAL_CHK_NULL(pRenderHal->pOsInterface->pOsContext); + MHW_RENDERHAL_CHK_NULL(pRenderHal->pfnGetOcaSupport); //----------------------------------------- - eStatus = MOS_STATUS_SUCCESS; - pStateHeap = pRenderHal->pStateHeap; + eStatus = MOS_STATUS_SUCCESS; + pStateHeap = pRenderHal->pStateHeap; + pOsInterface = pRenderHal->pOsInterface; + pOsContext = pOsInterface->pOsContext; + pRenderhalOcaSupport = &pRenderHal->pfnGetOcaSupport(); IdLoadParams.pKernelState = nullptr; IdLoadParams.dwInterfaceDescriptorStartOffset = pStateHeap->pCurMediaState->dwOffset + pStateHeap->dwOffsetMediaID; @@ -4364,6 +4389,9 @@ MOS_STATUS RenderHal_SendMediaIdLoad( MHW_RENDERHAL_CHK_STATUS(pRenderHal->pMhwRenderInterface->AddMediaIDLoadCmd(pCmdBuffer, &IdLoadParams)); + pRenderhalOcaSupport->OnIndirectState(*pCmdBuffer, *pOsContext, pRenderHal->StateBaseAddressParams.presDynamicState, + IdLoadParams.dwInterfaceDescriptorStartOffset, false, IdLoadParams.dwInterfaceDescriptorLength); + finish: return eStatus; } @@ -4547,6 +4575,8 @@ MOS_STATUS RenderHal_SendPredicationCommand( MHW_RENDERHAL_CHK_NULL(pRenderHal); MHW_RENDERHAL_CHK_NULL(pRenderHal->pOsInterface); MHW_RENDERHAL_CHK_NULL(pRenderHal->pMhwMiInterface); + MHW_RENDERHAL_CHK_NULL(pRenderHal->pMhwRenderInterface); + MHW_RENDERHAL_CHK_NULL(pRenderHal->pMhwRenderInterface->GetMmioRegisters()); //----------------------------------------- MHW_MI_CONDITIONAL_BATCH_BUFFER_END_PARAMS condBBEndParams; @@ -4570,7 +4600,7 @@ MOS_STATUS RenderHal_SendPredicationCommand( // Skip current frame if presPredication is not equal to zero if (pRenderHal->PredicationParams.predicationNotEqualZero) { - auto mmioRegistersRender = pRenderHal->pMhwMiInterface->GetMmioRegisters(); + auto mmioRegistersRender = pRenderHal->pMhwRenderInterface->GetMmioRegisters(); MHW_MI_FLUSH_DW_PARAMS flushDwParams; MOS_ZeroMemory(&flushDwParams, sizeof(flushDwParams)); MHW_RENDERHAL_CHK_STATUS(pRenderHal->pMhwMiInterface->AddMiFlushDwCmd(pCmdBuffer, &flushDwParams)); @@ -4686,7 +4716,7 @@ MOS_STATUS RenderHal_SendPredicationCommand( } else { - auto mmioRegistersRender = pRenderHal->pMhwMiInterface->GetMmioRegisters(); + auto mmioRegistersRender = pRenderHal->pMhwRenderInterface->GetMmioRegisters(); MHW_MI_FLUSH_DW_PARAMS flushDwParams; MOS_ZeroMemory(&flushDwParams, sizeof(flushDwParams)); @@ -5268,12 +5298,17 @@ MOS_STATUS RenderHal_SendMediaStates( PMHW_WALKER_PARAMS pWalkerParams, PMHW_GPGPU_WALKER_PARAMS pGpGpuWalkerParams) { - PMOS_INTERFACE pOsInterface; - MhwRenderInterface *pMhwRender; - PMHW_MI_INTERFACE pMhwMiInterface; - PRENDERHAL_STATE_HEAP pStateHeap; - MOS_STATUS eStatus; + PMOS_INTERFACE pOsInterface = nullptr; + MhwRenderInterface *pMhwRender = nullptr; + PMHW_MI_INTERFACE pMhwMiInterface = nullptr; + PRENDERHAL_STATE_HEAP pStateHeap = nullptr; + MOS_STATUS eStatus = MOS_STATUS_SUCCESS; MHW_VFE_PARAMS *pVfeStateParams = nullptr; + MOS_CONTEXT *pOsContext = nullptr; + MHW_MI_LOAD_REGISTER_IMM_PARAMS loadRegisterImmParams = {}; + PMHW_MI_MMIOREGISTERS pMmioRegisters = nullptr; + MOS_OCA_BUFFER_HANDLE hOcaBuf = 0; + RenderhalOcaSupport *pRenderhalOcaSupport = nullptr; //--------------------------------------- MHW_RENDERHAL_CHK_NULL(pRenderHal); @@ -5282,11 +5317,17 @@ MOS_STATUS RenderHal_SendMediaStates( MHW_RENDERHAL_CHK_NULL(pRenderHal->pStateHeap); MHW_RENDERHAL_CHK_NULL(pRenderHal->pRenderHalPltInterface); MHW_RENDERHAL_ASSERT(pRenderHal->pStateHeap->bGshLocked); + MHW_RENDERHAL_CHK_NULL(pRenderHal->pMhwRenderInterface->GetMmioRegisters()); + MHW_RENDERHAL_CHK_NULL(pRenderHal->pfnGetOcaSupport); + //--------------------------------------- - pOsInterface = pRenderHal->pOsInterface; - pMhwRender = pRenderHal->pMhwRenderInterface; - pMhwMiInterface = pRenderHal->pMhwMiInterface; - pStateHeap = pRenderHal->pStateHeap; + pOsInterface = pRenderHal->pOsInterface; + pMhwRender = pRenderHal->pMhwRenderInterface; + pMhwMiInterface = pRenderHal->pMhwMiInterface; + pStateHeap = pRenderHal->pStateHeap; + pOsContext = pOsInterface->pOsContext; + pMmioRegisters = pMhwRender->GetMmioRegisters(); + pRenderhalOcaSupport = &pRenderHal->pfnGetOcaSupport(); // This need not be secure, since PPGTT will be used here. But moving this after // L3 cache configuration will delay UMD from fetching another media state. @@ -5309,6 +5350,10 @@ MOS_STATUS RenderHal_SendMediaStates( MHW_RENDERHAL_CHK_STATUS(pMhwRender->AddPipelineSelectCmd(pCmdBuffer, (pGpGpuWalkerParams) ? true: false)); + // The binding table for surface states is at end of command buffer. No need to add it to indirect state heap. + pRenderhalOcaSupport->OnIndirectState(*pCmdBuffer, *pOsContext, pRenderHal->StateBaseAddressParams.presInstructionBuffer, + pStateHeap->CurIDEntryParams.dwKernelOffset, false, pStateHeap->iKernelUsedForDump); + // Send State Base Address command MHW_RENDERHAL_CHK_STATUS(pRenderHal->pfnSendStateBaseAddress(pRenderHal, pCmdBuffer)); @@ -5357,6 +5402,8 @@ MOS_STATUS RenderHal_SendMediaStates( // Send Palettes in use MHW_RENDERHAL_CHK_STATUS(pRenderHal->pfnSendPalette(pRenderHal, pCmdBuffer)); + pRenderhalOcaSupport->OnDispatch(*pCmdBuffer, *pOsContext, *pRenderHal->pMhwMiInterface, *pMmioRegisters); + // Send Media object walker if(pWalkerParams) { @@ -5633,38 +5680,40 @@ MOS_STATUS RenderHal_SetupInterfaceDescriptor( PRENDERHAL_INTERFACE_DESCRIPTOR_PARAMS pInterfaceDescriptorParams) { MOS_STATUS eStatus = MOS_STATUS_SUCCESS; - MHW_ID_ENTRY_PARAMS Params; - PRENDERHAL_STATE_HEAP pStateHeap; + PMHW_ID_ENTRY_PARAMS pParams = nullptr; + PRENDERHAL_STATE_HEAP pStateHeap = nullptr; //----------------------------------------- MHW_RENDERHAL_CHK_NULL(pRenderHal); MHW_RENDERHAL_CHK_NULL(pRenderHal->pMhwStateHeap); + MHW_RENDERHAL_CHK_NULL(pRenderHal->pStateHeap); MHW_RENDERHAL_CHK_NULL(pMediaState); MHW_RENDERHAL_CHK_NULL(pKernelAllocation); MHW_RENDERHAL_CHK_NULL(pInterfaceDescriptorParams); //----------------------------------------- // Get states, params - pStateHeap = pRenderHal->pStateHeap; + pStateHeap = pRenderHal->pStateHeap; + pParams = &pStateHeap->CurIDEntryParams; - Params.dwMediaIdOffset = pMediaState->dwOffset + pStateHeap->dwOffsetMediaID; - Params.iMediaId = pInterfaceDescriptorParams->iMediaID; - Params.dwKernelOffset = pKernelAllocation->dwOffset; - Params.dwSamplerOffset = pMediaState->dwOffset + pStateHeap->dwOffsetSampler + + pParams->dwMediaIdOffset = pMediaState->dwOffset + pStateHeap->dwOffsetMediaID; + pParams->iMediaId = pInterfaceDescriptorParams->iMediaID; + pParams->dwKernelOffset = pKernelAllocation->dwOffset; + pParams->dwSamplerOffset = pMediaState->dwOffset + pStateHeap->dwOffsetSampler + pInterfaceDescriptorParams->iMediaID * pStateHeap->dwSizeSampler; - Params.dwSamplerCount = pKernelAllocation->Params.Sampler_Count; - Params.dwBindingTableOffset = pInterfaceDescriptorParams->iBindingTableID * pStateHeap->iBindingTableSize; - Params.iCurbeOffset = pInterfaceDescriptorParams->iCurbeOffset; - Params.iCurbeLength = pInterfaceDescriptorParams->iCurbeLength; + pParams->dwSamplerCount = pKernelAllocation->Params.Sampler_Count; + pParams->dwBindingTableOffset = pInterfaceDescriptorParams->iBindingTableID * pStateHeap->iBindingTableSize; + pParams->iCurbeOffset = pInterfaceDescriptorParams->iCurbeOffset; + pParams->iCurbeLength = pInterfaceDescriptorParams->iCurbeLength; - Params.bBarrierEnable = pInterfaceDescriptorParams->blBarrierEnable; - Params.bGlobalBarrierEnable = pInterfaceDescriptorParams->blGlobalBarrierEnable; //It's only applied for BDW+ - Params.dwNumberofThreadsInGPGPUGroup = pInterfaceDescriptorParams->iNumberThreadsInGroup; - Params.dwSharedLocalMemorySize = pRenderHal->pfnEncodeSLMSize(pRenderHal, pInterfaceDescriptorParams->iSLMSize); - Params.iCrsThdConDataRdLn = pInterfaceDescriptorParams->iCrsThrdConstDataLn; - Params.pGeneralStateHeap = nullptr; + pParams->bBarrierEnable = pInterfaceDescriptorParams->blBarrierEnable; + pParams->bGlobalBarrierEnable = pInterfaceDescriptorParams->blGlobalBarrierEnable; //It's only applied for BDW+ + pParams->dwNumberofThreadsInGPGPUGroup = pInterfaceDescriptorParams->iNumberThreadsInGroup; + pParams->dwSharedLocalMemorySize = pRenderHal->pfnEncodeSLMSize(pRenderHal, pInterfaceDescriptorParams->iSLMSize); + pParams->iCrsThdConDataRdLn = pInterfaceDescriptorParams->iCrsThrdConstDataLn; + pParams->pGeneralStateHeap = nullptr; - MHW_RENDERHAL_CHK_STATUS(pRenderHal->pMhwStateHeap->SetInterfaceDescriptorEntry(&Params)); + MHW_RENDERHAL_CHK_STATUS(pRenderHal->pMhwStateHeap->SetInterfaceDescriptorEntry(pParams)); finish: return eStatus; @@ -6958,6 +7007,7 @@ MOS_STATUS RenderHal_InitInterface( pRenderHal->pfnSendRcsStatusTag = RenderHal_SendRcsStatusTag; pRenderHal->pfnSendSyncTag = RenderHal_SendSyncTag; pRenderHal->pfnSendCscCoeffSurface = RenderHal_SendCscCoeffSurface; + pRenderHal->pfnGetOcaSupport = RenderHal_GetOcaSupport; // Tracker tag pRenderHal->pfnSetupPrologParams = RenderHal_SetupPrologParams; diff --git a/media_driver/agnostic/common/renderhal/renderhal.h b/media_driver/agnostic/common/renderhal/renderhal.h index fe2fe016150..2fcefcb46b3 100644 --- a/media_driver/agnostic/common/renderhal/renderhal.h +++ b/media_driver/agnostic/common/renderhal/renderhal.h @@ -39,6 +39,7 @@ #include "mhw_memory_pool.h" #include "cm_hal_hashtable.h" #include "media_perf_profiler.h" +#include "renderhal_oca_support.h" #include "frame_tracker.h" @@ -880,6 +881,8 @@ typedef struct _RENDERHAL_STATE_HEAP uint32_t dwOffsetMediaID; // Offset to Media IDs from Media State Base uint32_t dwSizeMediaID; // Size of each Media ID + MHW_ID_ENTRY_PARAMS CurIDEntryParams = {}; // Parameters for current Interface Descriptor Entry + // Performance capture uint32_t dwOffsetStartTime; // Offset to the start time of the media state uint32_t dwStartTimeSize; // Size of Start time @@ -952,6 +955,7 @@ typedef struct _RENDERHAL_STATE_HEAP int32_t iKernelUsed; // Kernel heap used size uint8_t *pKernelLoadMap; // Kernel load map uint32_t dwAccessCounter; // Incremented when a kernel is loaded/used, for dynamic allocation + int32_t iKernelUsedForDump; // Kernel heap used size without alignment data in tail. // Kernel Spill Area uint32_t dwScratchSpaceSize; // Size of the Scratch Area @@ -1710,6 +1714,8 @@ typedef struct _RENDERHAL_INTERFACE bool(*pfnPerThreadScratchSpaceStart2K) ( PRENDERHAL_INTERFACE pRenderHal); + RenderhalOcaSupport &(* pfnGetOcaSupport)(); + //--------------------------- // Overwrite L3 Cache control register //--------------------------- @@ -1881,6 +1887,12 @@ MOS_STATUS RenderHal_SendTimingData( PMOS_COMMAND_BUFFER pCmdBuffer, bool bStartTime); +//! +//! \brief Get Oca support object +//! \return RenderhalOcaSupport& +//! +RenderhalOcaSupport &RenderHal_GetOcaSupport(); + // Constants defined in RenderHal interface extern const MHW_PIPE_CONTROL_PARAMS g_cRenderHal_InitPipeControlParams; extern const MHW_VFE_PARAMS g_cRenderHal_InitVfeParams; diff --git a/media_driver/agnostic/common/renderhal/renderhal_dsh.cpp b/media_driver/agnostic/common/renderhal/renderhal_dsh.cpp index a935d290e66..3f56f025243 100644 --- a/media_driver/agnostic/common/renderhal/renderhal_dsh.cpp +++ b/media_driver/agnostic/common/renderhal/renderhal_dsh.cpp @@ -2842,6 +2842,12 @@ MOS_STATUS RenderHal_DSH_SendTimingData( PMOS_COMMAND_BUFFER pCmdBuffer, bool bStartTime); +//! +//! \brief Get Oca support object +//! \return RenderhalOcaSupport& +//! +RenderhalOcaSupport &RenderHal_DSH_GetOcaSupport(); + //! Following functions are defined in RenderHal and are not used by RenderHal_DSH //! ------------------------------------------------------------------------------ PRENDERHAL_MEDIA_STATE RenderHal_DSH_AssignMediaState( @@ -2986,6 +2992,7 @@ MOS_STATUS RenderHal_InitInterface_Dynamic( pRenderHal->pfnReset = RenderHal_DSH_Reset; pRenderHal->pfnSendTimingData = RenderHal_DSH_SendTimingData; pRenderHal->pfnSendSyncTag = RenderHal_DSH_SendSyncTag; + pRenderHal->pfnGetOcaSupport = RenderHal_DSH_GetOcaSupport; // Sampler state, interface descriptor, VFE params pRenderHal->pfnSetSamplerStates = RenderHal_DSH_SetSamplerStates; diff --git a/media_driver/agnostic/common/renderhal/renderhal_oca_support.cpp b/media_driver/agnostic/common/renderhal/renderhal_oca_support.cpp new file mode 100644 index 00000000000..064c1a68988 --- /dev/null +++ b/media_driver/agnostic/common/renderhal/renderhal_oca_support.cpp @@ -0,0 +1,198 @@ +/* +* Copyright (c) 2019, Intel Corporation +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +*/ +//! +//! \file renderhal_oca_support.cpp +//! \brief Implementation of functions for Renderhal OCA support +//! + +#include "stdint.h" +#include "mos_os.h" +#include "renderhal_oca_support.h" +#include "mhw_mmio.h" + +/****************************************************************************************************/ +/* RenderhalOcaSupport */ +/****************************************************************************************************/ + +//! +//! \brief Oca operation which should be called at the beginning of 1st level batch buffer start. +//! \param [in/out] cmdBuffer +//! Command buffer for current BB. hOcaBuf in cmdBuffer will be updated. +//! \param [in] mosContext +//! Reference to MOS_CONTEXT. +//! \param [in] gpuContextHandle +//! Gpu context handle +//! \param [in] mhwMiInterface +//! Reference to MhwMiInterface. +//! \param [in] mmioRegisters +//! mmio registers for current engine. +//! \param [in] offsetOf1stLevelBB +//! Offset for current BB in cmdBuffer. +//! \param [in] bUseSizeOfCmdBuf +//! If true, use size of cmdBuffer for batch buffer, else use sizeOf1stLevelBB. +//! \param [in] sizeOf1stLevelBB +//! Size of BB. Ignore if bUseSizeOfResource == true. +//! \return void +//! No return value. Handle all exception inside the function. +//! +void RenderhalOcaSupport::On1stLevelBBStart(MOS_COMMAND_BUFFER &cmdBuffer, MOS_CONTEXT &mosContext, + uint32_t gpuContextHandle, MhwMiInterface &mhwMiInterface, MHW_MI_MMIOREGISTERS &mmioRegisters, + uint32_t offsetOf1stLevelBB, bool bUseSizeOfCmdBuf, uint32_t sizeOf1stLevelBB) +{ +} + +//! +//! \brief Oca operation which should be called before adding batch buffer end command for 1st +//! level batch buffer. +//! \param [in/out] cmdBuffer +//! Command buffer for current BB. hOcaBuf in cmdBuffer will be updated. +//! \param [in] mosContext +//! Reference to MOS_CONTEXT. +//! \return void +//! No return value. Handle all exception inside the function. +//! +void RenderhalOcaSupport::On1stLevelBBEnd(MOS_COMMAND_BUFFER &cmdBuffer, MOS_CONTEXT &mosContext) +{ +} + +//! +//! \brief Oca operation which should be called before sending start sub level batch buffer command. +//! \param [in] cmdBuffer +//! Command buffer for current BB. +//! \param [in] mosContext +//! Reference to MOS_CONTEXT. +//! \param [in] pMosResource +//! Pointer to the MOS_RESOURCE. +//! \param [in] offsetOfSubLevelBB +//! Offset for current BB in pMosResource. +//! \param [in] bUseSizeOfResource +//! If true, use size of pMosResource for batch buffer, else use sizeOfIndirectState. +//! \param [in] sizeOfSubLevelBB +//! Size of BB. Ignore if bUseSizeOfResource == true. +//! \return void +//! No return value. Handle all exception inside the function. +//! +void RenderhalOcaSupport::OnSubLevelBBStart(MOS_COMMAND_BUFFER &cmdBuffer, MOS_CONTEXT &mosContext, void *pMosResource, uint32_t offsetOfSubLevelBB, bool bUseSizeOfResource, uint32_t sizeOfSubLevelBB) +{ +} + +//! +//! \brief Oca operation which should be called when indirect states being added. +//! \param [in] cmdBuffer +//! Command buffer for current BB. +//! \param [in] mosContext +//! Reference to MOS_CONTEXT. +//! \param [in] pMosResource +//! Pointer to the MOS_RESOURCE. +//! \param [in] offsetOfIndirectState +//! Offset for current state in pMosResource. +//! \param [in] bUseSizeOfResource +//! If true, use size of pMosResource for indirect state, else use sizeOfIndirectState. +//! \param [in] sizeOfIndirectState +//! Size of indirect state. Ignore if bUseSizeOfResource == true. +//! \return void +//! No return value. Handle all exception inside the function. +//! +void RenderhalOcaSupport::OnIndirectState(MOS_COMMAND_BUFFER &cmdBuffer, MOS_CONTEXT &mosContext, void *pMosResource, uint32_t offsetOfIndirectState, bool bUseSizeOfResource, uint32_t sizeOfIndirectState) +{ +} + +//! +//! \brief Oca operation which should be called before adding dispatch states, +//! e.g. VEB_DI_IECP_STATE and MEDIA_OBJECT_WALKER. +//! \param [in] cmdBuffer +//! Command buffer for current BB. +//! \param [in] mosContext +//! Reference to MOS_CONTEXT. +//! \param [in] mhwMiInterface +//! Reference to MhwMiInterface. +//! \param [in] mmioRegisters +//! mmio registers for current engine. +//! \return void +//! No return value. Handle all exception inside the function. +//! +void RenderhalOcaSupport::OnDispatch(MOS_COMMAND_BUFFER &cmdBuffer, MOS_CONTEXT &mosContext, MhwMiInterface &mhwMiInterface, MHW_MI_MMIOREGISTERS &mmioRegisters) +{ +} + +//! +//! \brief Add string to oca log section +//! \param [in] cmdBuffer +//! Command buffer for current BB. +//! \param [in] mosContext +//! Reference to MOS_CONTEXT. +//! \param [in] str +//! string to be added. +//! \param [in] maxCount +//! size of the buffer pointed by str. +//! \return void +//! No return value. Handle all exception inside the function. +//! +void RenderhalOcaSupport::TraceMessage(MOS_COMMAND_BUFFER &cmdBuffer, MOS_CONTEXT &mosContext, const char *str, uint32_t maxCount) +{ +} + +//! +//! \brief Add vp kernel info to oca log section. +//! \param [in] cmdBuffer +//! Command buffer for current BB. +//! \param [in] mosContext +//! Reference to MOS_CONTEXT. +//! \param [in] vpKernelID +//! Value of enum VpKernelID. +//! \param [in] fcKernelCount +//! If vpKernelID == kernelCombinedFc, fcKernelCount is the kernel count for fc, otherwise, it's not used. +//! \param [in] fcKernelList +//! If vpKernelID == kernelCombinedFc, fcKernelList is the kernel list for fc, otherwise, it's not used. +//! \return void +//! No return value. Handle all exception inside the function. +//! +void RenderhalOcaSupport::DumpVpKernelInfo(MOS_COMMAND_BUFFER &cmdBuffer, MOS_CONTEXT &mosContext, int vpKernelID, int fcKernelCount, int *fcKernelList) +{ +} + + +RenderhalOcaSupport::~RenderhalOcaSupport() +{ +} + +RenderhalOcaSupport &RenderhalOcaSupport::GetInstance() +{ + static RenderhalOcaSupport instance; + return instance; +} + +/****************************************************************************************************/ +/* Private functions to ensure class singleton. */ +/****************************************************************************************************/ +RenderhalOcaSupport::RenderhalOcaSupport() +{ +} + +RenderhalOcaSupport::RenderhalOcaSupport(RenderhalOcaSupport &) +{ +} + +RenderhalOcaSupport& RenderhalOcaSupport::operator= (RenderhalOcaSupport &) +{ + return *this; +} diff --git a/media_driver/agnostic/common/renderhal/renderhal_oca_support.h b/media_driver/agnostic/common/renderhal/renderhal_oca_support.h new file mode 100644 index 00000000000..e470e6a9813 --- /dev/null +++ b/media_driver/agnostic/common/renderhal/renderhal_oca_support.h @@ -0,0 +1,175 @@ +/* +* Copyright (c) 2019, Intel Corporation +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +*/ +//! +//! \file renderhal_oca_support.h +//! \brief Implementation of functions for Renderhal OCA support +//! +#ifndef __RENDERHAL_OCA_SUPPORT_H__ +#define __RENDERHAL_OCA_SUPPORT_H__ + +/****************************************************************************************************/ +/* RenderhalOcaSupport */ +/****************************************************************************************************/ + +#include "mhw_mmio.h" +#include "mhw_mi.h" + +class RenderhalOcaSupport +{ +public: + //! + //! \brief Destructor + //! + virtual ~RenderhalOcaSupport(); + + //! + //! \brief Oca operation which should be called at the beginning of 1st level batch buffer start. + //! \param [in/out] cmdBuffer + //! Command buffer for current BB. hOcaBuf in cmdBuffer will be updated. + //! \param [in] mosContext + //! Reference to MOS_CONTEXT. + //! \param [in] gpuContextHandle + //! Gpu context handle + //! \param [in] mhwMiInterface + //! Reference to MhwMiInterface. + //! \param [in] mmioRegisters + //! mmio registers for current engine. + //! \param [in] offsetOf1stLevelBB + //! Offset for current BB in cmdBuffer. + //! \param [in] bUseSizeOfCmdBuf + //! If true, use size of cmdBuffer for batch buffer, else use sizeOf1stLevelBB. + //! \param [in] sizeOf1stLevelBB + //! Size of BB. Ignore if bUseSizeOfResource == true. + //! \return void + //! No return value. Handle all exception inside the function. + //! + virtual void On1stLevelBBStart(MOS_COMMAND_BUFFER &cmdBuffer, MOS_CONTEXT &mosContext, + uint32_t gpuContextHandle, MhwMiInterface &mhwMiInterface, MHW_MI_MMIOREGISTERS &mmioRegisters, + uint32_t offsetOf1stLevelBB = 0, bool bUseSizeOfCmdBuf = true, uint32_t sizeOf1stLevelBB = 0); + + //! + //! \brief Oca operation which should be called before adding batch buffer end command for 1st + //! level batch buffer. + //! \param [in/out] cmdBuffer + //! Command buffer for current BB. hOcaBuf in cmdBuffer will be updated. + //! \param [in] mosContext + //! Reference to MOS_CONTEXT. + //! \return void + //! No return value. Handle all exception inside the function. + //! + virtual void On1stLevelBBEnd(MOS_COMMAND_BUFFER &cmdBuffer, MOS_CONTEXT &mosContext); + + //! + //! \brief Oca operation which should be called before sending start sub level batch buffer command. + //! \param [in] cmdBuffer + //! Command buffer for current BB. + //! \param [in] mosContext + //! Reference to MOS_CONTEXT. + //! \param [in] pMosResource + //! Pointer to the MOS_RESOURCE. + //! \param [in] offsetOfSubLevelBB + //! Offset for current BB in pMosResource. + //! \param [in] bUseSizeOfResource + //! If true, use size of pMosResource for batch buffer, else use sizeOfIndirectState. + //! \param [in] sizeOfSubLevelBB + //! Size of BB. Ignore if bUseSizeOfResource == true. + //! \return void + //! No return value. Handle all exception inside the function. + //! + virtual void OnSubLevelBBStart(MOS_COMMAND_BUFFER &cmdBuffer, MOS_CONTEXT &mosContext, void *pMosResource, uint32_t offsetOfSubLevelBB, bool bUseSizeOfResource, uint32_t sizeOfSubLevelBB); + + //! + //! \brief Oca operation which should be called when indirect states being added. + //! \param [in] cmdBuffer + //! Command buffer for current BB. + //! \param [in] mosContext + //! Reference to MOS_CONTEXT. + //! \param [in] pMosResource + //! Pointer to the MOS_RESOURCE. + //! \param [in] offsetOfIndirectState + //! Offset for current state in pMosResource. + //! \param [in] bUseSizeOfResource + //! If true, use size of pMosResource for indirect state, else use sizeOfIndirectState. + //! \param [in] sizeOfIndirectState + //! Size of indirect state. Ignore if bUseSizeOfResource == true. + //! \return void + //! No return value. Handle all exception inside the function. + //! + virtual void OnIndirectState(MOS_COMMAND_BUFFER &cmdBuffer, MOS_CONTEXT &mosContext, void *pMosResource, uint32_t offsetOfIndirectState, bool bUseSizeOfResource, uint32_t sizeOfIndirectState); + + //! + //! \brief Oca operation which should be called before adding dispatch states, + //! e.g. VEB_DI_IECP_STATE and MEDIA_OBJECT_WALKER. + //! \param [in] cmdBuffer + //! Command buffer for current BB. + //! \param [in] mosContext + //! Reference to MOS_CONTEXT. + //! \param [in] mhwMiInterface + //! Reference to MhwMiInterface. + //! \param [in] mmioRegisters + //! mmio registers for current engine. + //! \return void + //! No return value. Handle all exception inside the function. + //! + virtual void OnDispatch(MOS_COMMAND_BUFFER &cmdBuffer, MOS_CONTEXT &mosContext, MhwMiInterface &mhwMiInterface, MHW_MI_MMIOREGISTERS &mmioRegisters); + + //! + //! \brief Add string to oca log section + //! \param [in] cmdBuffer + //! Command buffer for current BB. + //! \param [in] mosContext + //! Reference to MOS_CONTEXT. + //! \param [in] str + //! string to be added. + //! \param [in] maxCount + //! size of the buffer pointed by str. + //! \return void + //! No return value. Handle all exception inside the function. + //! + virtual void TraceMessage(MOS_COMMAND_BUFFER &cmdBuffer, MOS_CONTEXT &mosContext, const char *str, uint32_t maxCount); + + //! + //! \brief Add vp kernel info to oca log section. + //! \param [in] cmdBuffer + //! Command buffer for current BB. + //! \param [in] mosContext + //! Reference to MOS_CONTEXT. + //! \param [in] vpKernelID + //! Value of enum VpKernelID. + //! \param [in] fcKernelCount + //! If vpKernelID == kernelCombinedFc, fcKernelCount is the kernel count for fc, otherwise, it's not used. + //! \param [in] fcKernelList + //! If vpKernelID == kernelCombinedFc, fcKernelList is the kernel list for fc, otherwise, it's not used. + //! \return void + //! No return value. Handle all exception inside the function. + //! + virtual void DumpVpKernelInfo(MOS_COMMAND_BUFFER &cmdBuffer, MOS_CONTEXT &mosContext, int vpKernelID, int fcKernelCount, int *fcKernelList); + + static RenderhalOcaSupport& GetInstance(); +protected: + // Private functions to ensure class singleton. + RenderhalOcaSupport(); + RenderhalOcaSupport(RenderhalOcaSupport &); + RenderhalOcaSupport& operator= (RenderhalOcaSupport &); +}; + +#endif // __RENDERHAL_OCA_SUPPORT_H__ diff --git a/media_driver/agnostic/common/vp/hal/vphal_render_16alignment.cpp b/media_driver/agnostic/common/vp/hal/vphal_render_16alignment.cpp index 8198f00d0e8..9065dae5392 100644 --- a/media_driver/agnostic/common/vp/hal/vphal_render_16alignment.cpp +++ b/media_driver/agnostic/common/vp/hal/vphal_render_16alignment.cpp @@ -949,6 +949,8 @@ MOS_STATUS VpHal_16AlignRender( nullptr, &p16AlignState->StatusTableUpdateParams, kernelUserPtr, + 0, + nullptr, true)); finish: diff --git a/media_driver/agnostic/common/vp/hal/vphal_render_common.c b/media_driver/agnostic/common/vp/hal/vphal_render_common.c index 912cc914f4c..57ed55942d9 100644 --- a/media_driver/agnostic/common/vp/hal/vphal_render_common.c +++ b/media_driver/agnostic/common/vp/hal/vphal_render_common.c @@ -28,6 +28,7 @@ #include "vphal_render_composite.h" #include "mos_os.h" #include "mos_solo_generic.h" +#include "renderhal_oca_support.h" extern const MEDIA_OBJECT_KA2_INLINE_DATA g_cInit_MEDIA_OBJECT_KA2_INLINE_DATA = { @@ -416,18 +417,29 @@ MOS_STATUS VpHal_RndrCommonSubmitCommands( VpKernelID KernelID, bool bLastSubmission) { - PMOS_INTERFACE pOsInterface; - MOS_COMMAND_BUFFER CmdBuffer; - MOS_STATUS eStatus; - uint32_t dwSyncTag; - int32_t i, iRemaining; - PMHW_MI_INTERFACE pMhwMiInterface; - MhwRenderInterface *pMhwRender; - MHW_MEDIA_STATE_FLUSH_PARAM FlushParam; - bool bEnableSLM; + PMOS_INTERFACE pOsInterface = nullptr; + MOS_COMMAND_BUFFER CmdBuffer = {}; + MOS_STATUS eStatus = MOS_STATUS_SUCCESS; + uint32_t dwSyncTag = 0; + int32_t i = 0, iRemaining = 0; + PMHW_MI_INTERFACE pMhwMiInterface = nullptr; + MhwRenderInterface *pMhwRender = nullptr; + MHW_MEDIA_STATE_FLUSH_PARAM FlushParam = {}; + bool bEnableSLM = false; RENDERHAL_GENERIC_PROLOG_PARAMS GenericPrologParams = {}; - MOS_RESOURCE GpuStatusBuffer; - MediaPerfProfiler *pPerfProfiler; + MOS_RESOURCE GpuStatusBuffer = {}; + MediaPerfProfiler *pPerfProfiler = nullptr; + MOS_CONTEXT *pOsContext = nullptr; + PMHW_MI_MMIOREGISTERS pMmioRegisters = nullptr; + RenderhalOcaSupport *pRenderhalOcaSupport = nullptr; + + MHW_RENDERHAL_CHK_NULL(pRenderHal); + MHW_RENDERHAL_CHK_NULL(pRenderHal->pMhwRenderInterface); + MHW_RENDERHAL_CHK_NULL(pRenderHal->pMhwMiInterface); + MHW_RENDERHAL_CHK_NULL(pRenderHal->pMhwRenderInterface->GetMmioRegisters()); + MHW_RENDERHAL_CHK_NULL(pRenderHal->pOsInterface); + MHW_RENDERHAL_CHK_NULL(pRenderHal->pOsInterface->pOsContext); + MHW_RENDERHAL_CHK_NULL(pRenderHal->pfnGetOcaSupport); eStatus = MOS_STATUS_UNKNOWN; pOsInterface = pRenderHal->pOsInterface; @@ -437,6 +449,9 @@ MOS_STATUS VpHal_RndrCommonSubmitCommands( FlushParam = g_cRenderHal_InitMediaStateFlushParams; MOS_ZeroMemory(&CmdBuffer, sizeof(CmdBuffer)); pPerfProfiler = pRenderHal->pPerfProfiler; + pOsContext = pOsInterface->pOsContext; + pMmioRegisters = pMhwRender->GetMmioRegisters(); + pRenderhalOcaSupport = &pRenderHal->pfnGetOcaSupport(); // Allocate all available space, unused buffer will be returned later VPHAL_RENDER_CHK_STATUS(pOsInterface->pfnGetCommandBuffer(pOsInterface, &CmdBuffer, 0)); @@ -469,6 +484,10 @@ MOS_STATUS VpHal_RndrCommonSubmitCommands( // Initialize command buffer and insert prolog VPHAL_RENDER_CHK_STATUS(pRenderHal->pfnInitCommandBuffer(pRenderHal, &CmdBuffer, &GenericPrologParams)); + + pRenderhalOcaSupport->On1stLevelBBStart(CmdBuffer, *pOsContext, pOsInterface->CurrentGpuContextHandle, + *pRenderHal->pMhwMiInterface, *pMmioRegisters); + // Write timing data for 3P budget VPHAL_RENDER_CHK_STATUS(pRenderHal->pfnSendTimingData(pRenderHal, &CmdBuffer, true)); VPHAL_RENDER_CHK_STATUS(pPerfProfiler->AddPerfCollectStartCmd((void*)pRenderHal, pOsInterface, pMhwMiInterface, &CmdBuffer)); @@ -495,6 +514,8 @@ MOS_STATUS VpHal_RndrCommonSubmitCommands( false, true)); + pRenderhalOcaSupport->OnSubLevelBBStart(CmdBuffer, *pOsContext, &pBatchBuffer->OsResource, 0, true, 0); + // Send Start 2nd level batch buffer command (HW/OS dependent) VPHAL_RENDER_CHK_STATUS(pMhwMiInterface->AddMiBatchBufferStartCmd( &CmdBuffer, @@ -553,6 +574,8 @@ MOS_STATUS VpHal_RndrCommonSubmitCommands( } } + pRenderhalOcaSupport->On1stLevelBBEnd(CmdBuffer, *pOsContext); + if (pBatchBuffer) { // Send Batch Buffer end command (HW/OS dependent) @@ -611,7 +634,10 @@ MOS_STATUS VpHal_RndrCommonSubmitCommands( CmdBuffer.pCmdBase + CmdBuffer.iOffset / sizeof(uint32_t); // Return unused command buffer space to OS - pOsInterface->pfnReturnCommandBuffer(pOsInterface, &CmdBuffer, 0); + if (pOsInterface) + { + pOsInterface->pfnReturnCommandBuffer(pOsInterface, &CmdBuffer, 0); + } } return eStatus; @@ -634,6 +660,10 @@ MOS_STATUS VpHal_RndrCommonSubmitCommands( //! Pointer to pStatusTableUpdateParams //! \param [in] KernelID //! VP Kernel ID +//! \param [in] FcKernelCount +//! VP FC Kernel Count +//! \param [in] FcKernelList +//! VP FC Kernel List //! \param [in] bLastSubmission //! Is last submission //! \return MOS_STATUS @@ -646,20 +676,33 @@ MOS_STATUS VpHal_RndrSubmitCommands( PMHW_GPGPU_WALKER_PARAMS pGpGpuWalkerParams, PSTATUS_TABLE_UPDATE_PARAMS pStatusTableUpdateParams, VpKernelID KernelID, + int FcKernelCount, + int *FcKernelList, bool bLastSubmission) { - PMOS_INTERFACE pOsInterface; - MOS_COMMAND_BUFFER CmdBuffer; - MOS_STATUS eStatus; - uint32_t dwSyncTag; - int32_t i, iRemaining; - PMHW_MI_INTERFACE pMhwMiInterface; - MhwRenderInterface *pMhwRender; - MHW_MEDIA_STATE_FLUSH_PARAM FlushParam; - bool bEnableSLM; + PMOS_INTERFACE pOsInterface = nullptr; + MOS_COMMAND_BUFFER CmdBuffer = {}; + MOS_STATUS eStatus = MOS_STATUS_SUCCESS; + uint32_t dwSyncTag = 0; + int32_t i = 0, iRemaining = 0; + PMHW_MI_INTERFACE pMhwMiInterface = nullptr; + MhwRenderInterface *pMhwRender = nullptr; + MHW_MEDIA_STATE_FLUSH_PARAM FlushParam = {}; + bool bEnableSLM = false; RENDERHAL_GENERIC_PROLOG_PARAMS GenericPrologParams = {}; - MOS_RESOURCE GpuStatusBuffer; - MediaPerfProfiler *pPerfProfiler; + MOS_RESOURCE GpuStatusBuffer = {}; + MediaPerfProfiler *pPerfProfiler = nullptr; + MOS_CONTEXT *pOsContext = nullptr; + PMHW_MI_MMIOREGISTERS pMmioRegisters = nullptr; + RenderhalOcaSupport *pRenderhalOcaSupport = nullptr; + + MHW_RENDERHAL_CHK_NULL(pRenderHal); + MHW_RENDERHAL_CHK_NULL(pRenderHal->pMhwRenderInterface); + MHW_RENDERHAL_CHK_NULL(pRenderHal->pMhwMiInterface); + MHW_RENDERHAL_CHK_NULL(pRenderHal->pMhwRenderInterface->GetMmioRegisters()); + MHW_RENDERHAL_CHK_NULL(pRenderHal->pOsInterface); + MHW_RENDERHAL_CHK_NULL(pRenderHal->pOsInterface->pOsContext); + MHW_RENDERHAL_CHK_NULL(pRenderHal->pfnGetOcaSupport); eStatus = MOS_STATUS_UNKNOWN; pOsInterface = pRenderHal->pOsInterface; @@ -669,10 +712,19 @@ MOS_STATUS VpHal_RndrSubmitCommands( FlushParam = g_cRenderHal_InitMediaStateFlushParams; MOS_ZeroMemory(&CmdBuffer, sizeof(CmdBuffer)); pPerfProfiler = pRenderHal->pPerfProfiler; + pOsContext = pOsInterface->pOsContext; + pMmioRegisters = pMhwRender->GetMmioRegisters(); + pRenderhalOcaSupport = &pRenderHal->pfnGetOcaSupport(); // Allocate all available space, unused buffer will be returned later VPHAL_RENDER_CHK_STATUS(pOsInterface->pfnGetCommandBuffer(pOsInterface, &CmdBuffer, 0)); + pRenderhalOcaSupport->On1stLevelBBStart(CmdBuffer, *pOsContext, pOsInterface->CurrentGpuContextHandle, + *pRenderHal->pMhwMiInterface, *pMmioRegisters); + + // Add kernel info to log. + pRenderhalOcaSupport->DumpVpKernelInfo(CmdBuffer, *pOsContext, KernelID, FcKernelCount, FcKernelList); + // Set initial state iRemaining = CmdBuffer.iRemaining; @@ -736,6 +788,8 @@ MOS_STATUS VpHal_RndrSubmitCommands( &pBatchBuffer->OsResource, false, true)); + + pRenderhalOcaSupport->OnSubLevelBBStart(CmdBuffer, *pOsContext, &pBatchBuffer->OsResource, 0, true, 0); // Send Start 2nd level batch buffer command (HW/OS dependent) VPHAL_RENDER_CHK_STATUS(pMhwMiInterface->AddMiBatchBufferStartCmd( @@ -795,6 +849,8 @@ MOS_STATUS VpHal_RndrSubmitCommands( } } + pRenderhalOcaSupport->On1stLevelBBEnd(CmdBuffer, *pOsContext); + if (pBatchBuffer) { // Send Batch Buffer end command (HW/OS dependent) @@ -868,7 +924,10 @@ MOS_STATUS VpHal_RndrSubmitCommands( CmdBuffer.pCmdBase + CmdBuffer.iOffset / sizeof(uint32_t); // Return unused command buffer space to OS - pOsInterface->pfnReturnCommandBuffer(pOsInterface, &CmdBuffer, 0); + if (pOsInterface) + { + pOsInterface->pfnReturnCommandBuffer(pOsInterface, &CmdBuffer, 0); + } } return eStatus; diff --git a/media_driver/agnostic/common/vp/hal/vphal_render_common.h b/media_driver/agnostic/common/vp/hal/vphal_render_common.h index 821ae555c06..9e945227590 100644 --- a/media_driver/agnostic/common/vp/hal/vphal_render_common.h +++ b/media_driver/agnostic/common/vp/hal/vphal_render_common.h @@ -2589,6 +2589,10 @@ MOS_STATUS VpHal_RndrCommonSubmitCommands( //! Pointer to pStatusTableUpdateParams //! \param [in] KernelID //! VP Kernel ID +//! \param [in] FcKernelCount +//! VP FC Kernel Count +//! \param [in] FcKernelList +//! VP FC Kernel List //! \param [in] bLastSubmission //! whether it is the last submission //! \return MOS_STATUS @@ -2601,6 +2605,8 @@ MOS_STATUS VpHal_RndrSubmitCommands( PMHW_GPGPU_WALKER_PARAMS pGpGpuWalkerParams, PSTATUS_TABLE_UPDATE_PARAMS pStatusTableUpdateParams, VpKernelID KernelID, + int FcKernelCount, + int *FcKernelList, bool bLastSubmission); //! diff --git a/media_driver/agnostic/common/vp/hal/vphal_render_composite.cpp b/media_driver/agnostic/common/vp/hal/vphal_render_composite.cpp index c4bf52252ef..f46d13e224a 100644 --- a/media_driver/agnostic/common/vp/hal/vphal_render_composite.cpp +++ b/media_driver/agnostic/common/vp/hal/vphal_render_composite.cpp @@ -5957,6 +5957,10 @@ MOS_STATUS CompositeState::RenderPhase( goto finish; } } + else + { + VPHAL_RENDER_NORMALMESSAGE("Use previous kernel list."); + } RenderingData.bCmFcEnable = pKernelDllState->bEnableCMFC ? true : false; @@ -6127,6 +6131,8 @@ MOS_STATUS CompositeState::RenderPhase( pComputeWalkerParams, &m_StatusTableUpdateParams, kernelCombinedFc, + m_KernelSearch.KernelCount, + m_KernelSearch.KernelID, m_bLastPhase)); finish: diff --git a/media_driver/agnostic/common/vp/hal/vphal_render_fast1ton.cpp b/media_driver/agnostic/common/vp/hal/vphal_render_fast1ton.cpp index ecdaa3d116f..a8b099afe74 100644 --- a/media_driver/agnostic/common/vp/hal/vphal_render_fast1ton.cpp +++ b/media_driver/agnostic/common/vp/hal/vphal_render_fast1ton.cpp @@ -910,6 +910,8 @@ MOS_STATUS VpHal_Fast1toNRender( nullptr, &pFast1toNState->StatusTableUpdateParams, kernelFast1toN, + 0, + nullptr, true)); finish: diff --git a/media_driver/agnostic/common/vp/hal/vphal_render_vebox_base.cpp b/media_driver/agnostic/common/vp/hal/vphal_render_vebox_base.cpp index 9a0160efbbc..add686ac3c0 100644 --- a/media_driver/agnostic/common/vp/hal/vphal_render_vebox_base.cpp +++ b/media_driver/agnostic/common/vp/hal/vphal_render_vebox_base.cpp @@ -1816,16 +1816,27 @@ MOS_STATUS VPHAL_VEBOX_STATE::VeboxRenderVeboxCmd( MHW_MI_FLUSH_DW_PARAMS& FlushDwParams, PRENDERHAL_GENERIC_PROLOG_PARAMS pGenericPrologParams) { - MOS_STATUS eStatus; - PRENDERHAL_INTERFACE pRenderHal; - PMOS_INTERFACE pOsInterface; - PMHW_MI_INTERFACE pMhwMiInterface; - PMHW_VEBOX_INTERFACE pVeboxInterface; - bool bDiVarianceEnable; + MOS_STATUS eStatus = MOS_STATUS_SUCCESS; + PRENDERHAL_INTERFACE pRenderHal = nullptr; + PMOS_INTERFACE pOsInterface = nullptr; + PMHW_MI_INTERFACE pMhwMiInterface = nullptr; + PMHW_VEBOX_INTERFACE pVeboxInterface = nullptr; + bool bDiVarianceEnable = false; const MHW_VEBOX_HEAP *pVeboxHeap = nullptr; PVPHAL_VEBOX_STATE pVeboxState = this; PVPHAL_VEBOX_RENDER_DATA pRenderData = GetLastExecRenderData(); - MediaPerfProfiler *pPerfProfiler; + MediaPerfProfiler *pPerfProfiler = nullptr; + MOS_CONTEXT *pOsContext = nullptr; + PMHW_MI_MMIOREGISTERS pMmioRegisters = nullptr; + RenderhalOcaSupport *pRenderhalOcaSupport = nullptr; + + MHW_RENDERHAL_CHK_NULL(pVeboxState); + MHW_RENDERHAL_CHK_NULL(pVeboxState->m_pRenderHal); + MHW_RENDERHAL_CHK_NULL(pVeboxState->m_pRenderHal->pMhwMiInterface); + MHW_RENDERHAL_CHK_NULL(pVeboxState->m_pRenderHal->pMhwMiInterface->GetMmioRegisters()); + MHW_RENDERHAL_CHK_NULL(pVeboxState->m_pRenderHal->pOsInterface); + MHW_RENDERHAL_CHK_NULL(pVeboxState->m_pRenderHal->pOsInterface->pOsContext); + MHW_RENDERHAL_CHK_NULL(pVeboxState->m_pRenderHal->pfnGetOcaSupport); eStatus = MOS_STATUS_SUCCESS; pRenderHal = pVeboxState->m_pRenderHal; @@ -1833,6 +1844,9 @@ MOS_STATUS VPHAL_VEBOX_STATE::VeboxRenderVeboxCmd( pOsInterface = pVeboxState->m_pOsInterface; pVeboxInterface = pVeboxState->m_pVeboxInterface; pPerfProfiler = pRenderHal->pPerfProfiler; + pOsContext = pOsInterface->pOsContext; + pMmioRegisters = pMhwMiInterface->GetMmioRegisters(); + pRenderhalOcaSupport = &pRenderHal->pfnGetOcaSupport(); VPHAL_RENDER_CHK_STATUS(pVeboxInterface->GetVeboxHeapInfo( &pVeboxHeap)); @@ -1841,6 +1855,9 @@ MOS_STATUS VPHAL_VEBOX_STATE::VeboxRenderVeboxCmd( // Initialize command buffer and insert prolog VPHAL_RENDER_CHK_STATUS(pRenderHal->pfnInitCommandBuffer(pRenderHal, &CmdBuffer, pGenericPrologParams)); + pRenderhalOcaSupport->On1stLevelBBStart(CmdBuffer, *pOsContext, pOsInterface->CurrentGpuContextHandle, + *pRenderHal->pMhwMiInterface, *pMmioRegisters); + VPHAL_RENDER_CHK_STATUS(pPerfProfiler->AddPerfCollectStartCmd((void*)pRenderHal, pOsInterface, pRenderHal->pMhwMiInterface, &CmdBuffer)); bDiVarianceEnable = pRenderData->bDeinterlace || IsQueryVarianceEnabled(); @@ -1959,6 +1976,8 @@ MOS_STATUS VPHAL_VEBOX_STATE::VeboxRenderVeboxCmd( &CmdBuffer)); } + pRenderhalOcaSupport->OnDispatch(CmdBuffer, *pOsContext, *pRenderHal->pMhwMiInterface, *pMmioRegisters); + //--------------------------------- // Send CMD: Vebox_DI_IECP //--------------------------------- @@ -1995,6 +2014,8 @@ MOS_STATUS VPHAL_VEBOX_STATE::VeboxRenderVeboxCmd( VPHAL_RENDER_CHK_STATUS(pPerfProfiler->AddPerfCollectEndCmd((void*)pRenderHal, pOsInterface, pRenderHal->pMhwMiInterface, &CmdBuffer)); + pRenderhalOcaSupport->On1stLevelBBEnd(CmdBuffer, *pOsContext); + if (pOsInterface->bNoParsingAssistanceInKmd) { VPHAL_RENDER_CHK_STATUS(pMhwMiInterface->AddMiBatchBufferEnd( diff --git a/media_driver/agnostic/gen10/hw/mhw_mi_g10_X.cpp b/media_driver/agnostic/gen10/hw/mhw_mi_g10_X.cpp index dd03b3505a3..a68eb458d70 100644 --- a/media_driver/agnostic/gen10/hw/mhw_mi_g10_X.cpp +++ b/media_driver/agnostic/gen10/hw/mhw_mi_g10_X.cpp @@ -141,6 +141,10 @@ void MhwMiInterfaceG10::InitMmioRegisters() mmioRegisters->generalPurposeRegister0HiOffset = GP_REGISTER0_HI_OFFSET_G10; mmioRegisters->generalPurposeRegister4LoOffset = GP_REGISTER4_LO_OFFSET_G10; mmioRegisters->generalPurposeRegister4HiOffset = GP_REGISTER4_HI_OFFSET_G10; + mmioRegisters->generalPurposeRegister11LoOffset = GP_REGISTER11_LO_OFFSET_G10; + mmioRegisters->generalPurposeRegister11HiOffset = GP_REGISTER11_HI_OFFSET_G10; + mmioRegisters->generalPurposeRegister12LoOffset = GP_REGISTER12_LO_OFFSET_G10; + mmioRegisters->generalPurposeRegister12HiOffset = GP_REGISTER12_HI_OFFSET_G10; } MOS_STATUS MhwMiInterfaceG10::SetWatchdogTimerThreshold(uint32_t frameWidth, uint32_t frameHeight, bool isEncoder) diff --git a/media_driver/agnostic/gen10/hw/mhw_mmio_g10.h b/media_driver/agnostic/gen10/hw/mhw_mmio_g10.h index 65c0ff4893c..45e069845d3 100644 --- a/media_driver/agnostic/gen10/hw/mhw_mmio_g10.h +++ b/media_driver/agnostic/gen10/hw/mhw_mmio_g10.h @@ -28,11 +28,26 @@ #ifndef __MHW_MMIO_G10_H__ #define __MHW_MMIO_G10_H__ -//Common MI +// CS register offsets +#define CS_GENERAL_PURPOSE_REGISTER0_LO_OFFSET_G10 0x2600 +#define CS_GENERAL_PURPOSE_REGISTER0_HI_OFFSET_G10 0x2604 +#define CS_GENERAL_PURPOSE_REGISTER4_LO_OFFSET_G10 0x2620 +#define CS_GENERAL_PURPOSE_REGISTER4_HI_OFFSET_G10 0x2624 +#define CS_GENERAL_PURPOSE_REGISTER11_LO_OFFSET_G10 0x2658 +#define CS_GENERAL_PURPOSE_REGISTER11_HI_OFFSET_G10 0x265C +#define CS_GENERAL_PURPOSE_REGISTER12_LO_OFFSET_G10 0x2660 +#define CS_GENERAL_PURPOSE_REGISTER12_HI_OFFSET_G10 0x2664 + +// Vebox register offsets +// Used in Commen MI #define GP_REGISTER0_LO_OFFSET_G10 0x1A600 #define GP_REGISTER0_HI_OFFSET_G10 0x1A604 #define GP_REGISTER4_LO_OFFSET_G10 0x1A620 #define GP_REGISTER4_HI_OFFSET_G10 0x1A624 +#define GP_REGISTER11_LO_OFFSET_G10 0x1A658 +#define GP_REGISTER11_HI_OFFSET_G10 0x1A65C +#define GP_REGISTER12_LO_OFFSET_G10 0x1A660 +#define GP_REGISTER12_HI_OFFSET_G10 0x1A664 //VEBOX #define WATCHDOG_COUNT_CTRL_OFFSET_RCS_G10 0x2178 @@ -84,6 +99,10 @@ #define GENERAL_PURPOSE_REGISTER0_HI_OFFSET_NODE_1_INIT_G10 0x12604 #define GENERAL_PURPOSE_REGISTER4_LO_OFFSET_NODE_1_INIT_G10 0x12620 #define GENERAL_PURPOSE_REGISTER4_HI_OFFSET_NODE_1_INIT_G10 0x12624 +#define GENERAL_PURPOSE_REGISTER11_LO_OFFSET_NODE_1_INIT_G10 0x12658 +#define GENERAL_PURPOSE_REGISTER11_HI_OFFSET_NODE_1_INIT_G10 0x1265C +#define GENERAL_PURPOSE_REGISTER12_LO_OFFSET_NODE_1_INIT_G10 0x12660 +#define GENERAL_PURPOSE_REGISTER12_HI_OFFSET_NODE_1_INIT_G10 0x12664 #define MFC_IMAGE_STATUS_MASK_REG_OFFSET_NODE_1_INIT_G10 0x128B4 #define MFC_IMAGE_STATUS_CTRL_REG_OFFSET_NODE_1_INIT_G10 0x128B8 #define MFC_AVC_NUM_SLICES_REG_OFFSET_NODE_1_INIT_G10 0x12954 @@ -109,6 +128,10 @@ #define GENERAL_PURPOSE_REGISTER0_HI_OFFSET_NODE_2_INIT_G10 0x1C604 #define GENERAL_PURPOSE_REGISTER4_LO_OFFSET_NODE_2_INIT_G10 0x1C620 #define GENERAL_PURPOSE_REGISTER4_HI_OFFSET_NODE_2_INIT_G10 0x1C624 +#define GENERAL_PURPOSE_REGISTER11_LO_OFFSET_NODE_2_INIT_G10 0x1C658 +#define GENERAL_PURPOSE_REGISTER11_HI_OFFSET_NODE_2_INIT_G10 0x1C65C +#define GENERAL_PURPOSE_REGISTER12_LO_OFFSET_NODE_2_INIT_G10 0x1C660 +#define GENERAL_PURPOSE_REGISTER12_HI_OFFSET_NODE_2_INIT_G10 0x1C664 #define MFC_IMAGE_STATUS_MASK_REG_OFFSET_NODE_2_INIT_G10 0x1C8B4 #define MFC_IMAGE_STATUS_CTRL_REG_OFFSET_NODE_2_INIT_G10 0x1C8B8 #define MFC_AVC_NUM_SLICES_REG_OFFSET_NODE_2_INIT_G10 0x1C954 diff --git a/media_driver/agnostic/gen10/hw/mhw_render_g10_X.cpp b/media_driver/agnostic/gen10/hw/mhw_render_g10_X.cpp index 79e0d42eec9..0b35313b9bd 100644 --- a/media_driver/agnostic/gen10/hw/mhw_render_g10_X.cpp +++ b/media_driver/agnostic/gen10/hw/mhw_render_g10_X.cpp @@ -28,6 +28,7 @@ #include "mhw_render_g10_X.h" #include "mhw_render_hwcmd_g10_X.h" +#include "mhw_mmio_g10.h" MOS_STATUS MhwRenderInterfaceG10::AddMediaVfeCmd( PMOS_COMMAND_BUFFER cmdBuffer, @@ -290,3 +291,16 @@ MOS_STATUS MhwRenderInterfaceG10::AddGpgpuCsrBaseAddrCmd( return MOS_STATUS_SUCCESS; } + +void MhwRenderInterfaceG10::InitMmioRegisters() +{ + MHW_MI_MMIOREGISTERS *mmioRegisters = &m_mmioRegisters; + mmioRegisters->generalPurposeRegister0LoOffset = CS_GENERAL_PURPOSE_REGISTER0_LO_OFFSET_G10; + mmioRegisters->generalPurposeRegister0HiOffset = CS_GENERAL_PURPOSE_REGISTER0_HI_OFFSET_G10; + mmioRegisters->generalPurposeRegister4LoOffset = CS_GENERAL_PURPOSE_REGISTER4_LO_OFFSET_G10; + mmioRegisters->generalPurposeRegister4HiOffset = CS_GENERAL_PURPOSE_REGISTER4_HI_OFFSET_G10; + mmioRegisters->generalPurposeRegister11LoOffset = CS_GENERAL_PURPOSE_REGISTER11_LO_OFFSET_G10; + mmioRegisters->generalPurposeRegister11HiOffset = CS_GENERAL_PURPOSE_REGISTER11_HI_OFFSET_G10; + mmioRegisters->generalPurposeRegister12LoOffset = CS_GENERAL_PURPOSE_REGISTER12_LO_OFFSET_G10; + mmioRegisters->generalPurposeRegister12HiOffset = CS_GENERAL_PURPOSE_REGISTER12_HI_OFFSET_G10; +} diff --git a/media_driver/agnostic/gen10/hw/mhw_render_g10_X.h b/media_driver/agnostic/gen10/hw/mhw_render_g10_X.h index b4b6ee55085..6fe2b23f9af 100644 --- a/media_driver/agnostic/gen10/hw/mhw_render_g10_X.h +++ b/media_driver/agnostic/gen10/hw/mhw_render_g10_X.h @@ -46,6 +46,8 @@ class MhwRenderInterfaceG10 : public MhwRenderInterfaceGeneric // {SLM, URB, DC, RO(I/S, C, T), L3 Client Pool} // { 0, 64, 0, 0, 192 } m_l3CacheCntlRegisterValueDefault = 0xC0000040; + + InitMmioRegisters(); } virtual ~MhwRenderInterfaceG10() { MHW_FUNCTION_ENTER; } @@ -82,6 +84,15 @@ class MhwRenderInterfaceG10 : public MhwRenderInterfaceGeneric PMOS_COMMAND_BUFFER cmdBuffer ); MHW_RENDER_ENGINE_L3_CACHE_CONFIG* GetL3CacheConfig() { return &m_l3CacheConfig; } + + virtual PMHW_MI_MMIOREGISTERS GetMmioRegisters() + { + return &m_mmioRegisters; + } +private: + //! \brief Mmio registers address + MHW_MI_MMIOREGISTERS m_mmioRegisters = {}; + void InitMmioRegisters(); }; #endif diff --git a/media_driver/agnostic/gen10/hw/vdbox/mhw_vdbox_mfx_g10_X.cpp b/media_driver/agnostic/gen10/hw/vdbox/mhw_vdbox_mfx_g10_X.cpp index cbfc50ee9fc..2bc92984d7e 100644 --- a/media_driver/agnostic/gen10/hw/vdbox/mhw_vdbox_mfx_g10_X.cpp +++ b/media_driver/agnostic/gen10/hw/vdbox/mhw_vdbox_mfx_g10_X.cpp @@ -35,6 +35,10 @@ void MhwVdboxMfxInterfaceG10::InitMmioRegisters() mmioRegisters->generalPurposeRegister0HiOffset = GENERAL_PURPOSE_REGISTER0_HI_OFFSET_NODE_1_INIT_G10; mmioRegisters->generalPurposeRegister4LoOffset = GENERAL_PURPOSE_REGISTER4_LO_OFFSET_NODE_1_INIT_G10; mmioRegisters->generalPurposeRegister4HiOffset = GENERAL_PURPOSE_REGISTER4_HI_OFFSET_NODE_1_INIT_G10; + mmioRegisters->generalPurposeRegister11LoOffset = GENERAL_PURPOSE_REGISTER11_LO_OFFSET_NODE_1_INIT_G10; + mmioRegisters->generalPurposeRegister11HiOffset = GENERAL_PURPOSE_REGISTER11_HI_OFFSET_NODE_1_INIT_G10; + mmioRegisters->generalPurposeRegister12LoOffset = GENERAL_PURPOSE_REGISTER12_LO_OFFSET_NODE_1_INIT_G10; + mmioRegisters->generalPurposeRegister12HiOffset = GENERAL_PURPOSE_REGISTER12_HI_OFFSET_NODE_1_INIT_G10; mmioRegisters->mfcImageStatusMaskRegOffset = MFC_IMAGE_STATUS_MASK_REG_OFFSET_NODE_1_INIT_G10; mmioRegisters->mfcImageStatusCtrlRegOffset = MFC_IMAGE_STATUS_CTRL_REG_OFFSET_NODE_1_INIT_G10; mmioRegisters->mfcAvcNumSlicesRegOffset = MFC_AVC_NUM_SLICES_REG_OFFSET_NODE_1_INIT_G10; @@ -65,6 +69,10 @@ void MhwVdboxMfxInterfaceG10::InitMmioRegisters() mmioRegisters->generalPurposeRegister0HiOffset = GENERAL_PURPOSE_REGISTER0_HI_OFFSET_NODE_2_INIT_G10; mmioRegisters->generalPurposeRegister4LoOffset = GENERAL_PURPOSE_REGISTER4_LO_OFFSET_NODE_2_INIT_G10; mmioRegisters->generalPurposeRegister4HiOffset = GENERAL_PURPOSE_REGISTER4_HI_OFFSET_NODE_2_INIT_G10; + mmioRegisters->generalPurposeRegister11LoOffset = GENERAL_PURPOSE_REGISTER11_LO_OFFSET_NODE_2_INIT_G10; + mmioRegisters->generalPurposeRegister11HiOffset = GENERAL_PURPOSE_REGISTER11_HI_OFFSET_NODE_2_INIT_G10; + mmioRegisters->generalPurposeRegister12LoOffset = GENERAL_PURPOSE_REGISTER12_LO_OFFSET_NODE_2_INIT_G10; + mmioRegisters->generalPurposeRegister12HiOffset = GENERAL_PURPOSE_REGISTER12_HI_OFFSET_NODE_2_INIT_G10; mmioRegisters->mfcImageStatusMaskRegOffset = MFC_IMAGE_STATUS_MASK_REG_OFFSET_NODE_2_INIT_G10; mmioRegisters->mfcImageStatusCtrlRegOffset = MFC_IMAGE_STATUS_CTRL_REG_OFFSET_NODE_2_INIT_G10; mmioRegisters->mfcAvcNumSlicesRegOffset = MFC_AVC_NUM_SLICES_REG_OFFSET_NODE_2_INIT_G10; diff --git a/media_driver/agnostic/gen11/hw/mhw_mi_g11_X.cpp b/media_driver/agnostic/gen11/hw/mhw_mi_g11_X.cpp index c2570a10776..927a2145b21 100644 --- a/media_driver/agnostic/gen11/hw/mhw_mi_g11_X.cpp +++ b/media_driver/agnostic/gen11/hw/mhw_mi_g11_X.cpp @@ -424,4 +424,8 @@ void MhwMiInterfaceG11::InitMmioRegisters() mmioRegisters->generalPurposeRegister0HiOffset = GP_REGISTER0_HI_OFFSET_G11; mmioRegisters->generalPurposeRegister4LoOffset = GP_REGISTER4_LO_OFFSET_G11; mmioRegisters->generalPurposeRegister4HiOffset = GP_REGISTER4_HI_OFFSET_G11; + mmioRegisters->generalPurposeRegister11LoOffset = GP_REGISTER11_LO_OFFSET_G11; + mmioRegisters->generalPurposeRegister11HiOffset = GP_REGISTER11_HI_OFFSET_G11; + mmioRegisters->generalPurposeRegister12LoOffset = GP_REGISTER12_LO_OFFSET_G11; + mmioRegisters->generalPurposeRegister12HiOffset = GP_REGISTER12_HI_OFFSET_G11; } diff --git a/media_driver/agnostic/gen11/hw/mhw_mmio_g11.h b/media_driver/agnostic/gen11/hw/mhw_mmio_g11.h index e5fe674c33b..04356186f45 100644 --- a/media_driver/agnostic/gen11/hw/mhw_mmio_g11.h +++ b/media_driver/agnostic/gen11/hw/mhw_mmio_g11.h @@ -29,11 +29,27 @@ #ifndef __MHW_MMIO_G11_H__ #define __MHW_MMIO_G11_H__ -//Common MI + +// CS register offsets +#define CS_GENERAL_PURPOSE_REGISTER0_LO_OFFSET_G11 0x2600 +#define CS_GENERAL_PURPOSE_REGISTER0_HI_OFFSET_G11 0x2604 +#define CS_GENERAL_PURPOSE_REGISTER4_LO_OFFSET_G11 0x2620 +#define CS_GENERAL_PURPOSE_REGISTER4_HI_OFFSET_G11 0x2624 +#define CS_GENERAL_PURPOSE_REGISTER11_LO_OFFSET_G11 0x2658 +#define CS_GENERAL_PURPOSE_REGISTER11_HI_OFFSET_G11 0x265C +#define CS_GENERAL_PURPOSE_REGISTER12_LO_OFFSET_G11 0x2660 +#define CS_GENERAL_PURPOSE_REGISTER12_HI_OFFSET_G11 0x2664 + +// Vebox register offsets +// Used in Commen MI #define GP_REGISTER0_LO_OFFSET_G11 0x1C8600 #define GP_REGISTER0_HI_OFFSET_G11 0x1C8604 #define GP_REGISTER4_LO_OFFSET_G11 0x1C8620 #define GP_REGISTER4_HI_OFFSET_G11 0x1C8624 +#define GP_REGISTER11_LO_OFFSET_G11 0x1C8658 +#define GP_REGISTER11_HI_OFFSET_G11 0x1C865C +#define GP_REGISTER12_LO_OFFSET_G11 0x1C8660 +#define GP_REGISTER12_HI_OFFSET_G11 0x1C8664 //VEBOX #define WATCHDOG_COUNT_CTRL_OFFSET_RCS_G11 0x2178 @@ -78,6 +94,10 @@ #define GENERAL_PURPOSE_REGISTER0_HI_OFFSET_NODE_1_INIT_G11 0x1C0604 #define GENERAL_PURPOSE_REGISTER4_LO_OFFSET_NODE_1_INIT_G11 0x1C0620 #define GENERAL_PURPOSE_REGISTER4_HI_OFFSET_NODE_1_INIT_G11 0x1C0624 +#define GENERAL_PURPOSE_REGISTER11_LO_OFFSET_NODE_1_INIT_G11 0x1C0658 +#define GENERAL_PURPOSE_REGISTER11_HI_OFFSET_NODE_1_INIT_G11 0x1C065C +#define GENERAL_PURPOSE_REGISTER12_LO_OFFSET_NODE_1_INIT_G11 0x1C0660 +#define GENERAL_PURPOSE_REGISTER12_HI_OFFSET_NODE_1_INIT_G11 0x1C0664 #define MFC_IMAGE_STATUS_MASK_REG_OFFSET_NODE_1_INIT_G11 0x1C08B4 #define MFC_IMAGE_STATUS_CTRL_REG_OFFSET_NODE_1_INIT_G11 0x1C08B8 #define MFC_AVC_NUM_SLICES_REG_OFFSET_NODE_1_INIT_G11 0x1C0954 diff --git a/media_driver/agnostic/gen11/hw/mhw_render_g11_X.cpp b/media_driver/agnostic/gen11/hw/mhw_render_g11_X.cpp index f09b35d8804..463e10c546b 100644 --- a/media_driver/agnostic/gen11/hw/mhw_render_g11_X.cpp +++ b/media_driver/agnostic/gen11/hw/mhw_render_g11_X.cpp @@ -28,6 +28,7 @@ #include "mhw_render_g11_X.h" #include "mhw_render_hwcmd_g11_X.h" +#include "mhw_mmio_g11.h" MOS_STATUS MhwRenderInterfaceG11::AddMediaVfeCmd( PMOS_COMMAND_BUFFER cmdBuffer, @@ -235,3 +236,16 @@ MOS_STATUS MhwRenderInterfaceG11::AddGpgpuCsrBaseAddrCmd( return MOS_STATUS_SUCCESS; } + +void MhwRenderInterfaceG11::InitMmioRegisters() +{ + MHW_MI_MMIOREGISTERS *mmioRegisters = &m_mmioRegisters; + mmioRegisters->generalPurposeRegister0LoOffset = CS_GENERAL_PURPOSE_REGISTER0_LO_OFFSET_G11; + mmioRegisters->generalPurposeRegister0HiOffset = CS_GENERAL_PURPOSE_REGISTER0_HI_OFFSET_G11; + mmioRegisters->generalPurposeRegister4LoOffset = CS_GENERAL_PURPOSE_REGISTER4_LO_OFFSET_G11; + mmioRegisters->generalPurposeRegister4HiOffset = CS_GENERAL_PURPOSE_REGISTER4_HI_OFFSET_G11; + mmioRegisters->generalPurposeRegister11LoOffset = CS_GENERAL_PURPOSE_REGISTER11_LO_OFFSET_G11; + mmioRegisters->generalPurposeRegister11HiOffset = CS_GENERAL_PURPOSE_REGISTER11_HI_OFFSET_G11; + mmioRegisters->generalPurposeRegister12LoOffset = CS_GENERAL_PURPOSE_REGISTER12_LO_OFFSET_G11; + mmioRegisters->generalPurposeRegister12HiOffset = CS_GENERAL_PURPOSE_REGISTER12_HI_OFFSET_G11; +} diff --git a/media_driver/agnostic/gen11/hw/mhw_render_g11_X.h b/media_driver/agnostic/gen11/hw/mhw_render_g11_X.h index 79b87903614..250af6c82ee 100644 --- a/media_driver/agnostic/gen11/hw/mhw_render_g11_X.h +++ b/media_driver/agnostic/gen11/hw/mhw_render_g11_X.h @@ -57,6 +57,8 @@ class MhwRenderInterfaceG11 : public MhwRenderInterfaceGeneric // {SLM, URB, DC, RO(I/S, C, T), L3 Client Pool} // { 0, 64, 0, 0, 320 } m_l3CacheCntlRegisterValueDefault = 0xA0000620; + + InitMmioRegisters(); } virtual ~MhwRenderInterfaceG11() { MHW_FUNCTION_ENTER; } @@ -90,11 +92,21 @@ class MhwRenderInterfaceG11 : public MhwRenderInterfaceGeneric MHW_RENDER_ENGINE_L3_CACHE_CONFIG* GetL3CacheConfig() { return &m_l3CacheConfig; } + virtual PMHW_MI_MMIOREGISTERS GetMmioRegisters() + { + return &m_mmioRegisters; + } + protected: MHW_RENDER_ENGINE_L3_CACHE_CONFIG_G11 m_l3CacheConfig; uint32_t m_l3CacheTcCntlRegisterOffset = 0xB0A4; uint32_t m_l3CacheTcCntlRegisterValueDefault = 0x0000000D; + +private: + //! \brief Mmio registers address + MHW_MI_MMIOREGISTERS m_mmioRegisters = {}; + void InitMmioRegisters(); }; diff --git a/media_driver/agnostic/gen11/hw/vdbox/mhw_vdbox_mfx_g11_X.cpp b/media_driver/agnostic/gen11/hw/vdbox/mhw_vdbox_mfx_g11_X.cpp index 90f23a060b1..6428f8e17be 100644 --- a/media_driver/agnostic/gen11/hw/vdbox/mhw_vdbox_mfx_g11_X.cpp +++ b/media_driver/agnostic/gen11/hw/vdbox/mhw_vdbox_mfx_g11_X.cpp @@ -35,6 +35,10 @@ void MhwVdboxMfxInterfaceG11::InitMmioRegisters() mmioRegisters->generalPurposeRegister0HiOffset = GENERAL_PURPOSE_REGISTER0_HI_OFFSET_NODE_1_INIT_G11; mmioRegisters->generalPurposeRegister4LoOffset = GENERAL_PURPOSE_REGISTER4_LO_OFFSET_NODE_1_INIT_G11; mmioRegisters->generalPurposeRegister4HiOffset = GENERAL_PURPOSE_REGISTER4_HI_OFFSET_NODE_1_INIT_G11; + mmioRegisters->generalPurposeRegister11LoOffset = GENERAL_PURPOSE_REGISTER11_LO_OFFSET_NODE_1_INIT_G11; + mmioRegisters->generalPurposeRegister11HiOffset = GENERAL_PURPOSE_REGISTER11_HI_OFFSET_NODE_1_INIT_G11; + mmioRegisters->generalPurposeRegister12LoOffset = GENERAL_PURPOSE_REGISTER12_LO_OFFSET_NODE_1_INIT_G11; + mmioRegisters->generalPurposeRegister12HiOffset = GENERAL_PURPOSE_REGISTER12_HI_OFFSET_NODE_1_INIT_G11; mmioRegisters->mfcImageStatusMaskRegOffset = MFC_IMAGE_STATUS_MASK_REG_OFFSET_NODE_1_INIT_G11; mmioRegisters->mfcImageStatusCtrlRegOffset = MFC_IMAGE_STATUS_CTRL_REG_OFFSET_NODE_1_INIT_G11; mmioRegisters->mfcAvcNumSlicesRegOffset = MFC_AVC_NUM_SLICES_REG_OFFSET_NODE_1_INIT_G11; diff --git a/media_driver/agnostic/gen8/hw/mhw_mi_g8_X.cpp b/media_driver/agnostic/gen8/hw/mhw_mi_g8_X.cpp index 6f79379d31b..b965d3cd991 100644 --- a/media_driver/agnostic/gen8/hw/mhw_mi_g8_X.cpp +++ b/media_driver/agnostic/gen8/hw/mhw_mi_g8_X.cpp @@ -160,4 +160,8 @@ void MhwMiInterfaceG8::InitMmioRegisters() mmioRegisters->generalPurposeRegister0HiOffset = GP_REGISTER0_HI_OFFSET_G8; mmioRegisters->generalPurposeRegister4LoOffset = GP_REGISTER4_LO_OFFSET_G8; mmioRegisters->generalPurposeRegister4HiOffset = GP_REGISTER4_HI_OFFSET_G8; + mmioRegisters->generalPurposeRegister11LoOffset = GP_REGISTER11_LO_OFFSET_G8; + mmioRegisters->generalPurposeRegister11HiOffset = GP_REGISTER11_HI_OFFSET_G8; + mmioRegisters->generalPurposeRegister12LoOffset = GP_REGISTER12_LO_OFFSET_G8; + mmioRegisters->generalPurposeRegister12HiOffset = GP_REGISTER12_HI_OFFSET_G8; } diff --git a/media_driver/agnostic/gen8/hw/mhw_mmio_g8.h b/media_driver/agnostic/gen8/hw/mhw_mmio_g8.h index be6020ef1eb..bab302a8d75 100644 --- a/media_driver/agnostic/gen8/hw/mhw_mmio_g8.h +++ b/media_driver/agnostic/gen8/hw/mhw_mmio_g8.h @@ -29,18 +29,36 @@ #ifndef __MHW_MMIO_G8_H__ #define __MHW_MMIO_G8_H__ +// CS register offsets +#define CS_GENERAL_PURPOSE_REGISTER0_LO_OFFSET_G8 0x2600 +#define CS_GENERAL_PURPOSE_REGISTER0_HI_OFFSET_G8 0x2604 +#define CS_GENERAL_PURPOSE_REGISTER4_LO_OFFSET_G8 0x2620 +#define CS_GENERAL_PURPOSE_REGISTER4_HI_OFFSET_G8 0x2624 +#define CS_GENERAL_PURPOSE_REGISTER11_LO_OFFSET_G8 0x2658 +#define CS_GENERAL_PURPOSE_REGISTER11_HI_OFFSET_G8 0x265C +#define CS_GENERAL_PURPOSE_REGISTER12_LO_OFFSET_G8 0x2660 +#define CS_GENERAL_PURPOSE_REGISTER12_HI_OFFSET_G8 0x2664 -//Common MI +// Vebox register offsets +// Used in Commen MI #define GP_REGISTER0_LO_OFFSET_G8 0x1A600 #define GP_REGISTER0_HI_OFFSET_G8 0x1A604 #define GP_REGISTER4_LO_OFFSET_G8 0x1A620 #define GP_REGISTER4_HI_OFFSET_G8 0x1A624 +#define GP_REGISTER11_LO_OFFSET_G8 0x1A658 +#define GP_REGISTER11_HI_OFFSET_G8 0x1A65C +#define GP_REGISTER12_LO_OFFSET_G8 0x1A660 +#define GP_REGISTER12_HI_OFFSET_G8 0x1A664 //VDBOX MFX register offsets #define GENERAL_PURPOSE_REGISTER0_LO_OFFSET_NODE_1_INIT_G8 0x12600 #define GENERAL_PURPOSE_REGISTER0_HI_OFFSET_NODE_1_INIT_G8 0x12604 #define GENERAL_PURPOSE_REGISTER4_LO_OFFSET_NODE_1_INIT_G8 0x12620 #define GENERAL_PURPOSE_REGISTER4_HI_OFFSET_NODE_1_INIT_G8 0x12624 +#define GENERAL_PURPOSE_REGISTER11_LO_OFFSET_NODE_1_INIT_G8 0x12658 +#define GENERAL_PURPOSE_REGISTER11_HI_OFFSET_NODE_1_INIT_G8 0x1265C +#define GENERAL_PURPOSE_REGISTER12_LO_OFFSET_NODE_1_INIT_G8 0x12660 +#define GENERAL_PURPOSE_REGISTER12_HI_OFFSET_NODE_1_INIT_G8 0x12664 #define MFC_IMAGE_STATUS_MASK_REG_OFFSET_NODE_1_INIT_G8 0x128B4 #define MFC_IMAGE_STATUS_CTRL_REG_OFFSET_NODE_1_INIT_G8 0x128B8 #define MFC_QP_STATUS_COUNT_OFFSET_NODE_1_INIT_G8 0x128BC @@ -65,6 +83,10 @@ #define GENERAL_PURPOSE_REGISTER0_HI_OFFSET_NODE_2_INIT_G8 0x1C604 #define GENERAL_PURPOSE_REGISTER4_LO_OFFSET_NODE_2_INIT_G8 0x1C620 #define GENERAL_PURPOSE_REGISTER4_HI_OFFSET_NODE_2_INIT_G8 0x1C624 +#define GENERAL_PURPOSE_REGISTER11_LO_OFFSET_NODE_2_INIT_G8 0x1C658 +#define GENERAL_PURPOSE_REGISTER11_HI_OFFSET_NODE_2_INIT_G8 0x1C65C +#define GENERAL_PURPOSE_REGISTER12_LO_OFFSET_NODE_2_INIT_G8 0x1C660 +#define GENERAL_PURPOSE_REGISTER12_HI_OFFSET_NODE_2_INIT_G8 0x1C664 #define MFC_IMAGE_STATUS_MASK_REG_OFFSET_NODE_2_INIT_G8 0x1C8B4 #define MFC_IMAGE_STATUS_CTRL_REG_OFFSET_NODE_2_INIT_G8 0x1C8B8 #define MFC_QP_STATUS_COUNT_OFFSET_NODE_2_INIT_G8 0x1C8BC diff --git a/media_driver/agnostic/gen8/hw/mhw_render_g8_X.cpp b/media_driver/agnostic/gen8/hw/mhw_render_g8_X.cpp index 1f99ce452b6..bbe0c48a003 100644 --- a/media_driver/agnostic/gen8/hw/mhw_render_g8_X.cpp +++ b/media_driver/agnostic/gen8/hw/mhw_render_g8_X.cpp @@ -257,3 +257,17 @@ MOS_STATUS MhwRenderInterfaceG8::SetL3Cache( return eStatus; } + +void MhwRenderInterfaceG8::InitMmioRegisters() +{ + MHW_MI_MMIOREGISTERS *mmioRegisters = &m_mmioRegisters; + mmioRegisters->generalPurposeRegister0LoOffset = CS_GENERAL_PURPOSE_REGISTER0_LO_OFFSET_G8; + mmioRegisters->generalPurposeRegister0HiOffset = CS_GENERAL_PURPOSE_REGISTER0_HI_OFFSET_G8; + mmioRegisters->generalPurposeRegister4LoOffset = CS_GENERAL_PURPOSE_REGISTER4_LO_OFFSET_G8; + mmioRegisters->generalPurposeRegister4HiOffset = CS_GENERAL_PURPOSE_REGISTER4_HI_OFFSET_G8; + mmioRegisters->generalPurposeRegister11LoOffset = CS_GENERAL_PURPOSE_REGISTER11_LO_OFFSET_G8; + mmioRegisters->generalPurposeRegister11HiOffset = CS_GENERAL_PURPOSE_REGISTER11_HI_OFFSET_G8; + mmioRegisters->generalPurposeRegister12LoOffset = CS_GENERAL_PURPOSE_REGISTER12_LO_OFFSET_G8; + mmioRegisters->generalPurposeRegister12HiOffset = CS_GENERAL_PURPOSE_REGISTER12_HI_OFFSET_G8; +} + diff --git a/media_driver/agnostic/gen8/hw/mhw_render_g8_X.h b/media_driver/agnostic/gen8/hw/mhw_render_g8_X.h index 7ce575510c6..566d6290c99 100644 --- a/media_driver/agnostic/gen8/hw/mhw_render_g8_X.h +++ b/media_driver/agnostic/gen8/hw/mhw_render_g8_X.h @@ -56,6 +56,8 @@ struct MhwRenderInterfaceG8 : public MhwRenderInterfaceGeneric // SLM URB DC RO Rest // 0 256 0 0 512 (KB chunks based on GT2) m_l3CacheCntlRegisterValueDefault = 0x80000040; + + InitMmioRegisters(); } virtual ~MhwRenderInterfaceG8() { MHW_FUNCTION_ENTER; } @@ -88,6 +90,16 @@ struct MhwRenderInterfaceG8 : public MhwRenderInterfaceGeneric PMOS_COMMAND_BUFFER cmdBuffer ); MHW_RENDER_ENGINE_L3_CACHE_CONFIG* GetL3CacheConfig() { return &m_l3CacheConfig; } + + virtual PMHW_MI_MMIOREGISTERS GetMmioRegisters() + { + return &m_mmioRegisters; + } + +private: + //! \brief Mmio registers address + MHW_MI_MMIOREGISTERS m_mmioRegisters = {}; + void InitMmioRegisters(); }; #endif diff --git a/media_driver/agnostic/gen8/hw/vdbox/mhw_vdbox_mfx_g8_X.h b/media_driver/agnostic/gen8/hw/vdbox/mhw_vdbox_mfx_g8_X.h index 71aae9e2492..1cb9d3ed2cd 100644 --- a/media_driver/agnostic/gen8/hw/vdbox/mhw_vdbox_mfx_g8_X.h +++ b/media_driver/agnostic/gen8/hw/vdbox/mhw_vdbox_mfx_g8_X.h @@ -157,6 +157,10 @@ class MhwVdboxMfxInterfaceG8 : public MhwVdboxMfxInterfaceGenericgeneralPurposeRegister0HiOffset = GENERAL_PURPOSE_REGISTER0_HI_OFFSET_NODE_1_INIT_G8; mmioRegisters->generalPurposeRegister4LoOffset = GENERAL_PURPOSE_REGISTER4_LO_OFFSET_NODE_1_INIT_G8; mmioRegisters->generalPurposeRegister4HiOffset = GENERAL_PURPOSE_REGISTER4_HI_OFFSET_NODE_1_INIT_G8; + mmioRegisters->generalPurposeRegister11LoOffset = GENERAL_PURPOSE_REGISTER11_LO_OFFSET_NODE_1_INIT_G8; + mmioRegisters->generalPurposeRegister11HiOffset = GENERAL_PURPOSE_REGISTER11_HI_OFFSET_NODE_1_INIT_G8; + mmioRegisters->generalPurposeRegister12LoOffset = GENERAL_PURPOSE_REGISTER12_LO_OFFSET_NODE_1_INIT_G8; + mmioRegisters->generalPurposeRegister12HiOffset = GENERAL_PURPOSE_REGISTER12_HI_OFFSET_NODE_1_INIT_G8; mmioRegisters->mfcImageStatusMaskRegOffset = MFC_IMAGE_STATUS_MASK_REG_OFFSET_NODE_1_INIT_G8; mmioRegisters->mfcImageStatusCtrlRegOffset = MFC_IMAGE_STATUS_CTRL_REG_OFFSET_NODE_1_INIT_G8; mmioRegisters->mfcAvcNumSlicesRegOffset = MFC_AVC_NUM_SLICES_REG_OFFSET_NODE_1_INIT_G8; @@ -187,6 +191,10 @@ class MhwVdboxMfxInterfaceG8 : public MhwVdboxMfxInterfaceGenericgeneralPurposeRegister0HiOffset = GENERAL_PURPOSE_REGISTER0_HI_OFFSET_NODE_2_INIT_G8; mmioRegisters->generalPurposeRegister4LoOffset = GENERAL_PURPOSE_REGISTER4_LO_OFFSET_NODE_2_INIT_G8; mmioRegisters->generalPurposeRegister4HiOffset = GENERAL_PURPOSE_REGISTER4_HI_OFFSET_NODE_2_INIT_G8; + mmioRegisters->generalPurposeRegister11LoOffset = GENERAL_PURPOSE_REGISTER11_LO_OFFSET_NODE_2_INIT_G8; + mmioRegisters->generalPurposeRegister11HiOffset = GENERAL_PURPOSE_REGISTER11_HI_OFFSET_NODE_2_INIT_G8; + mmioRegisters->generalPurposeRegister12LoOffset = GENERAL_PURPOSE_REGISTER12_LO_OFFSET_NODE_2_INIT_G8; + mmioRegisters->generalPurposeRegister12HiOffset = GENERAL_PURPOSE_REGISTER12_HI_OFFSET_NODE_2_INIT_G8; mmioRegisters->mfcImageStatusMaskRegOffset = MFC_IMAGE_STATUS_MASK_REG_OFFSET_NODE_2_INIT_G8; mmioRegisters->mfcImageStatusCtrlRegOffset = MFC_IMAGE_STATUS_CTRL_REG_OFFSET_NODE_2_INIT_G8; mmioRegisters->mfcAvcNumSlicesRegOffset = MFC_AVC_NUM_SLICES_REG_OFFSET_NODE_2_INIT_G8; diff --git a/media_driver/agnostic/gen9/hw/mhw_mi_g9_X.cpp b/media_driver/agnostic/gen9/hw/mhw_mi_g9_X.cpp index b0bd165290b..11bb7523175 100644 --- a/media_driver/agnostic/gen9/hw/mhw_mi_g9_X.cpp +++ b/media_driver/agnostic/gen9/hw/mhw_mi_g9_X.cpp @@ -180,4 +180,8 @@ void MhwMiInterfaceG9::InitMmioRegisters() mmioRegisters->generalPurposeRegister0HiOffset = GP_REGISTER0_HI_OFFSET_G9; mmioRegisters->generalPurposeRegister4LoOffset = GP_REGISTER4_LO_OFFSET_G9; mmioRegisters->generalPurposeRegister4HiOffset = GP_REGISTER4_HI_OFFSET_G9; + mmioRegisters->generalPurposeRegister11LoOffset = GP_REGISTER11_LO_OFFSET_G9; + mmioRegisters->generalPurposeRegister11HiOffset = GP_REGISTER11_HI_OFFSET_G9; + mmioRegisters->generalPurposeRegister12LoOffset = GP_REGISTER12_LO_OFFSET_G9; + mmioRegisters->generalPurposeRegister12HiOffset = GP_REGISTER12_HI_OFFSET_G9; } diff --git a/media_driver/agnostic/gen9/hw/mhw_mmio_g9.h b/media_driver/agnostic/gen9/hw/mhw_mmio_g9.h index 5f68b8ba136..65fca95f39e 100644 --- a/media_driver/agnostic/gen9/hw/mhw_mmio_g9.h +++ b/media_driver/agnostic/gen9/hw/mhw_mmio_g9.h @@ -29,11 +29,26 @@ #define __MHW_MMIO_G9_H__ -//Common MI +// CS register offsets +#define CS_GENERAL_PURPOSE_REGISTER0_LO_OFFSET_G9 0x2600 +#define CS_GENERAL_PURPOSE_REGISTER0_HI_OFFSET_G9 0x2604 +#define CS_GENERAL_PURPOSE_REGISTER4_LO_OFFSET_G9 0x2620 +#define CS_GENERAL_PURPOSE_REGISTER4_HI_OFFSET_G9 0x2624 +#define CS_GENERAL_PURPOSE_REGISTER11_LO_OFFSET_G9 0x2658 +#define CS_GENERAL_PURPOSE_REGISTER11_HI_OFFSET_G9 0x265C +#define CS_GENERAL_PURPOSE_REGISTER12_LO_OFFSET_G9 0x2660 +#define CS_GENERAL_PURPOSE_REGISTER12_HI_OFFSET_G9 0x2664 + +// Vebox register offsets +// Used in Commen MI #define GP_REGISTER0_LO_OFFSET_G9 0x1A600 #define GP_REGISTER0_HI_OFFSET_G9 0x1A604 #define GP_REGISTER4_LO_OFFSET_G9 0x1A620 #define GP_REGISTER4_HI_OFFSET_G9 0x1A624 +#define GP_REGISTER11_LO_OFFSET_G9 0x1A658 +#define GP_REGISTER11_HI_OFFSET_G9 0x1A65C +#define GP_REGISTER12_LO_OFFSET_G9 0x1A660 +#define GP_REGISTER12_HI_OFFSET_G9 0x1A664 //VDBOX HCP register offsets #define HCP_ENC_IMAGE_STATUS_MASK_REG_OFFSET_INIT_G9 0x1E9B8 @@ -67,6 +82,10 @@ #define GENERAL_PURPOSE_REGISTER0_HI_OFFSET_NODE_1_INIT_G9 0x12604 #define GENERAL_PURPOSE_REGISTER4_LO_OFFSET_NODE_1_INIT_G9 0x12620 #define GENERAL_PURPOSE_REGISTER4_HI_OFFSET_NODE_1_INIT_G9 0x12624 +#define GENERAL_PURPOSE_REGISTER11_LO_OFFSET_NODE_1_INIT_G9 0x12658 +#define GENERAL_PURPOSE_REGISTER11_HI_OFFSET_NODE_1_INIT_G9 0x1265C +#define GENERAL_PURPOSE_REGISTER12_LO_OFFSET_NODE_1_INIT_G9 0x12660 +#define GENERAL_PURPOSE_REGISTER12_HI_OFFSET_NODE_1_INIT_G9 0x12664 #define MFC_IMAGE_STATUS_MASK_REG_OFFSET_NODE_1_INIT_G9 0x128B4 #define MFC_IMAGE_STATUS_CTRL_REG_OFFSET_NODE_1_INIT_G9 0x128B8 #define MFC_AVC_NUM_SLICES_REG_OFFSET_NODE_1_INIT_G9 0x12954 @@ -95,6 +114,10 @@ #define GENERAL_PURPOSE_REGISTER0_HI_OFFSET_NODE_2_INIT_G9 0x1C604 #define GENERAL_PURPOSE_REGISTER4_LO_OFFSET_NODE_2_INIT_G9 0x1C620 #define GENERAL_PURPOSE_REGISTER4_HI_OFFSET_NODE_2_INIT_G9 0x1C624 +#define GENERAL_PURPOSE_REGISTER11_LO_OFFSET_NODE_2_INIT_G9 0x1C658 +#define GENERAL_PURPOSE_REGISTER11_HI_OFFSET_NODE_2_INIT_G9 0x1C65C +#define GENERAL_PURPOSE_REGISTER12_LO_OFFSET_NODE_2_INIT_G9 0x1C660 +#define GENERAL_PURPOSE_REGISTER12_HI_OFFSET_NODE_2_INIT_G9 0x1C664 #define MFC_IMAGE_STATUS_MASK_REG_OFFSET_NODE_2_INIT_G9 0x1C8B4 #define MFC_IMAGE_STATUS_CTRL_REG_OFFSET_NODE_2_INIT_G9 0x1C8B8 #define MFC_AVC_NUM_SLICES_REG_OFFSET_NODE_2_INIT_G9 0x1C954 diff --git a/media_driver/agnostic/gen9/hw/mhw_render_g9_X.cpp b/media_driver/agnostic/gen9/hw/mhw_render_g9_X.cpp index 9086a56e5ab..742cba2511f 100644 --- a/media_driver/agnostic/gen9/hw/mhw_render_g9_X.cpp +++ b/media_driver/agnostic/gen9/hw/mhw_render_g9_X.cpp @@ -296,4 +296,17 @@ MOS_STATUS MhwRenderInterfaceG9::SetL3Cache( } return eStatus; -} \ No newline at end of file +} + +void MhwRenderInterfaceG9::InitMmioRegisters() +{ + MHW_MI_MMIOREGISTERS *mmioRegisters = &m_mmioRegisters; + mmioRegisters->generalPurposeRegister0LoOffset = CS_GENERAL_PURPOSE_REGISTER0_LO_OFFSET_G9; + mmioRegisters->generalPurposeRegister0HiOffset = CS_GENERAL_PURPOSE_REGISTER0_HI_OFFSET_G9; + mmioRegisters->generalPurposeRegister4LoOffset = CS_GENERAL_PURPOSE_REGISTER4_LO_OFFSET_G9; + mmioRegisters->generalPurposeRegister4HiOffset = CS_GENERAL_PURPOSE_REGISTER4_HI_OFFSET_G9; + mmioRegisters->generalPurposeRegister11LoOffset = CS_GENERAL_PURPOSE_REGISTER11_LO_OFFSET_G9; + mmioRegisters->generalPurposeRegister11HiOffset = CS_GENERAL_PURPOSE_REGISTER11_HI_OFFSET_G9; + mmioRegisters->generalPurposeRegister12LoOffset = CS_GENERAL_PURPOSE_REGISTER12_LO_OFFSET_G9; + mmioRegisters->generalPurposeRegister12HiOffset = CS_GENERAL_PURPOSE_REGISTER12_HI_OFFSET_G9; +} diff --git a/media_driver/agnostic/gen9/hw/mhw_render_g9_X.h b/media_driver/agnostic/gen9/hw/mhw_render_g9_X.h index e03133df983..2cc656743ea 100644 --- a/media_driver/agnostic/gen9/hw/mhw_render_g9_X.h +++ b/media_driver/agnostic/gen9/hw/mhw_render_g9_X.h @@ -61,6 +61,8 @@ class MhwRenderInterfaceG9 : public MhwRenderInterfaceGeneric // SLM URB DC RO Rest // 0 256 0 0 512 (KB chunks based on GT2) m_l3CacheCntlRegisterValueDefault = 0x80000040; + + InitMmioRegisters(); } virtual ~MhwRenderInterfaceG9() { MHW_FUNCTION_ENTER; } @@ -98,6 +100,15 @@ class MhwRenderInterfaceG9 : public MhwRenderInterfaceGeneric MHW_RENDER_ENGINE_L3_CACHE_CONFIG* GetL3CacheConfig() { return &m_l3CacheConfig; } + virtual PMHW_MI_MMIOREGISTERS GetMmioRegisters() + { + return &m_mmioRegisters; + } + +private: + //! \brief Mmio registers address + MHW_MI_MMIOREGISTERS m_mmioRegisters = {}; + void InitMmioRegisters(); }; #endif diff --git a/media_driver/agnostic/gen9/hw/vdbox/mhw_vdbox_mfx_g9_X.h b/media_driver/agnostic/gen9/hw/vdbox/mhw_vdbox_mfx_g9_X.h index 1d2e284df52..df894a64155 100644 --- a/media_driver/agnostic/gen9/hw/vdbox/mhw_vdbox_mfx_g9_X.h +++ b/media_driver/agnostic/gen9/hw/vdbox/mhw_vdbox_mfx_g9_X.h @@ -112,6 +112,10 @@ class MhwVdboxMfxInterfaceG9 : public MhwVdboxMfxInterfaceGenericgeneralPurposeRegister0HiOffset = GENERAL_PURPOSE_REGISTER0_HI_OFFSET_NODE_1_INIT_G9; mmioRegisters->generalPurposeRegister4LoOffset = GENERAL_PURPOSE_REGISTER4_LO_OFFSET_NODE_1_INIT_G9; mmioRegisters->generalPurposeRegister4HiOffset = GENERAL_PURPOSE_REGISTER4_HI_OFFSET_NODE_1_INIT_G9; + mmioRegisters->generalPurposeRegister11LoOffset = GENERAL_PURPOSE_REGISTER11_LO_OFFSET_NODE_1_INIT_G9; + mmioRegisters->generalPurposeRegister11HiOffset = GENERAL_PURPOSE_REGISTER11_HI_OFFSET_NODE_1_INIT_G9; + mmioRegisters->generalPurposeRegister12LoOffset = GENERAL_PURPOSE_REGISTER12_LO_OFFSET_NODE_1_INIT_G9; + mmioRegisters->generalPurposeRegister12HiOffset = GENERAL_PURPOSE_REGISTER12_HI_OFFSET_NODE_1_INIT_G9; mmioRegisters->mfcImageStatusMaskRegOffset = MFC_IMAGE_STATUS_MASK_REG_OFFSET_NODE_1_INIT_G9; mmioRegisters->mfcImageStatusCtrlRegOffset = MFC_IMAGE_STATUS_CTRL_REG_OFFSET_NODE_1_INIT_G9; mmioRegisters->mfcAvcNumSlicesRegOffset = MFC_AVC_NUM_SLICES_REG_OFFSET_NODE_1_INIT_G9; @@ -142,6 +146,10 @@ class MhwVdboxMfxInterfaceG9 : public MhwVdboxMfxInterfaceGenericgeneralPurposeRegister0HiOffset = GENERAL_PURPOSE_REGISTER0_HI_OFFSET_NODE_2_INIT_G9; mmioRegisters->generalPurposeRegister4LoOffset = GENERAL_PURPOSE_REGISTER4_LO_OFFSET_NODE_2_INIT_G9; mmioRegisters->generalPurposeRegister4HiOffset = GENERAL_PURPOSE_REGISTER4_HI_OFFSET_NODE_2_INIT_G9; + mmioRegisters->generalPurposeRegister11LoOffset = GENERAL_PURPOSE_REGISTER11_LO_OFFSET_NODE_2_INIT_G9; + mmioRegisters->generalPurposeRegister11HiOffset = GENERAL_PURPOSE_REGISTER11_HI_OFFSET_NODE_2_INIT_G9; + mmioRegisters->generalPurposeRegister12LoOffset = GENERAL_PURPOSE_REGISTER12_LO_OFFSET_NODE_2_INIT_G9; + mmioRegisters->generalPurposeRegister12HiOffset = GENERAL_PURPOSE_REGISTER12_HI_OFFSET_NODE_2_INIT_G9; mmioRegisters->mfcImageStatusMaskRegOffset = MFC_IMAGE_STATUS_MASK_REG_OFFSET_NODE_2_INIT_G9; mmioRegisters->mfcImageStatusCtrlRegOffset = MFC_IMAGE_STATUS_CTRL_REG_OFFSET_NODE_2_INIT_G9; mmioRegisters->mfcAvcNumSlicesRegOffset = MFC_AVC_NUM_SLICES_REG_OFFSET_NODE_2_INIT_G9; diff --git a/media_driver/linux/common/os/mos_os_specific.c b/media_driver/linux/common/os/mos_os_specific.c index 8d43ce01bdd..b558d4551b0 100644 --- a/media_driver/linux/common/os/mos_os_specific.c +++ b/media_driver/linux/common/os/mos_os_specific.c @@ -952,6 +952,11 @@ GMM_CLIENT_CONTEXT* Linux_GetGmmClientContext(PMOS_CONTEXT pOsContext) return pOsContext->pGmmClientContext; } +MosOcaInterface* Linux_GetOcaInterface() +{ + return nullptr; +} + //! //! \brief Get GPU tag for the given GPU context from the status buffer //! \details Get GPU tag for the given GPU context from the status buffer @@ -1435,6 +1440,7 @@ MOS_STATUS Linux_InitContext( pContext->pfnIncGpuCtxBufferTag = Linux_IncGpuCtxBufferTag; pContext->GetGPUTag = Linux_GetGPUTag; pContext->GetGmmClientContext = Linux_GetGmmClientContext; + pContext->GetOcaInterface = Linux_GetOcaInterface; finish: if (!modularizedGpuCtxEnabled) diff --git a/media_driver/linux/common/os/mos_os_specific.h b/media_driver/linux/common/os/mos_os_specific.h index 9ad0b98233f..e9403318f71 100644 --- a/media_driver/linux/common/os/mos_os_specific.h +++ b/media_driver/linux/common/os/mos_os_specific.h @@ -45,6 +45,7 @@ typedef unsigned int MOS_OS_FORMAT; class GraphicsResource; class AuxTableMgr; +class MosOcaInterface; //////////////////////////////////////////////////////////////////// @@ -600,6 +601,7 @@ struct _MOS_OS_CONTEXT GMM_CLIENT_CONTEXT* (* GetGmmClientContext)( PMOS_CONTEXT pOsContext); + MosOcaInterface* (*GetOcaInterface)(); }; //! diff --git a/media_driver/linux/common/renderhal/renderhal_dsh_specific.c b/media_driver/linux/common/renderhal/renderhal_dsh_specific.c index ed9d399b2cc..b7a73946ec7 100644 --- a/media_driver/linux/common/renderhal/renderhal_dsh_specific.c +++ b/media_driver/linux/common/renderhal/renderhal_dsh_specific.c @@ -39,3 +39,12 @@ MOS_STATUS RenderHal_DSH_SendTimingData( { return MOS_STATUS_SUCCESS; } + +//! +//! \brief Get Oca support object +//! \return RenderhalOcaSupport& +//! +RenderhalOcaSupport &RenderHal_DSH_GetOcaSupport() +{ + return RenderhalOcaSupport::GetInstance(); +} diff --git a/media_driver/linux/common/renderhal/renderhal_linux.cpp b/media_driver/linux/common/renderhal/renderhal_linux.cpp index f92a1d51164..7ae6b2a48dd 100644 --- a/media_driver/linux/common/renderhal/renderhal_linux.cpp +++ b/media_driver/linux/common/renderhal/renderhal_linux.cpp @@ -467,3 +467,12 @@ MOS_STATUS RenderHal_SendTimingData( { return MOS_STATUS_SUCCESS; } + +//! +//! \brief Get Oca support object +//! \return RenderhalOcaSupport& +//! +RenderhalOcaSupport &RenderHal_GetOcaSupport() +{ + return RenderhalOcaSupport::GetInstance(); +}