riscv-processor

RISCV processor in verilog.

Made for educational purposes.

Test programs are in risc_test_program.

Name		Name	Last commit message	Last commit date
Latest commit History 47 Commits
.github/workflows		.github/workflows
de10_lite		de10_lite
sim		sim
test_programs		test_programs
.gitignore		.gitignore
README.md		README.md
alu.v		alu.v
data_addr_bus_controller.v		data_addr_bus_controller.v
decode.v		decode.v
decode_logic.v		decode_logic.v
fetch.v		fetch.v
hazards.v		hazards.v
latch.v		latch.v
left_barrel_shifter.v		left_barrel_shifter.v
proc.v		proc.v
proc_params.h		proc_params.h
reg_dff.v		reg_dff.v
reg_file.v		reg_file.v
right_barrel_shifter.v		right_barrel_shifter.v
riscproccesorV1.xcf		riscproccesorV1.xcf
riscproccesorV2.xcf		riscproccesorV2.xcf

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