[verible-verilog-format] reported by reviewdog 🐶 Raw Output: decode.v:6:-module decode_register_select(a0, a1, a2, a2_hazard, imm_to_reg, imm_to_addr, func, en_jmp, en_uncond_jmp, en_rel_reg_jmp, decode.v:7:- en_mem_wr, ld_code, alu_data1, alu_data2, data_to_mem, en_reg_wr, dmem_addr_bus_use, decode.v:8:- instr, d0, d1, stall, squash, clk, rst); decode.v:9:- decode.v:10:- // Register identifiers for computation decode.v:11:- output wire [4:0] a0; decode.v:12:- output wire [4:0] a1; decode.v:13:- output wire [4:0] a2; decode.v:14:- output wire [4:0] a2_hazard; decode.v:15:- // Leaving decode stage, immediate values (if there is one) decode.v:16:- output wire [31:0] imm_to_reg; decode.v:17:- output wire [31:0] imm_to_addr; decode.v:18:- // Leaving decode stage, function value (if there is one) decode.v:19:- output wire [9:0] func; decode.v:20:- // Leaving decode stage, enables if a jump can be taken decode.v:21:- output wire en_jmp; decode.v:22:- // Leaving decode stage, enables unconditional jumps decode.v:23:- output wire en_uncond_jmp; decode.v:24:- // Leaving decode stage, enables unconditional jump relative to value in a register decode.v:25:- output wire en_rel_reg_jmp; decode.v:26:- // Leaving decode stage, enables a write to memory decode.v:27:- output wire en_mem_wr; decode.v:28:- // Leaving decode stage, value that determines which value is put on the register write bus decode.v:29:- output wire [2:0] ld_code; decode.v:30:- // Leaving decode stage, output data from register file decode.v:31:- output wire [31:0] alu_data1; decode.v:32:- output wire [31:0] alu_data2; decode.v:33:- // Leaving decode stage, data that is going to be written to memory decode.v:34:- output wire [31:0] data_to_mem; decode.v:35:- output wire en_reg_wr; decode.v:36:- output wire dmem_addr_bus_use; decode.v:37:- decode.v:38:- // From fetch stage, the fetched instruction decode.v:39:- input wire [31:0] instr; decode.v:40:- input wire [31:0] d0; decode.v:41:- input wire [31:0] d1; decode.v:42:- input wire stall; decode.v:43:- input wire squash; decode.v:44:- input wire clk, rst; decode.v:45:- decode.v:46:- // Enables immediates for computation decode.v:47:- wire en_imm; decode.v:48:- wire input_en_reg_wr; decode.v:49:- wire input_en_jmp; decode.v:50:- wire input_en_uncond_jmp; decode.v:51:- wire input_en_rel_reg_jmp; decode.v:52:- wire [9:0] input_func; decode.v:53:- reg [31:0] alu_input_data2; decode.v:54:- wire [31:0] input_imm; decode.v:55:- wire input_en_mem_wr; decode.v:56:- wire [2:0] input_ld_code; decode.v:57:- wire [4:0] input_a2; decode.v:58:- decode.v:59:- wire en_reg_wr_conn_latch1; decode.v:60:- wire en_reg_wr_conn_latch2; decode.v:61:- latch en_reg_wr_latch1 (.q(en_reg_wr_conn_latch1), .d(~squash & input_en_reg_wr), .stall(stall), .clk(clk), .rst(rst)); decode.v:62:- latch en_reg_wr_latch2 (.q(en_reg_wr_conn_latch2), .d(en_reg_wr_conn_latch1), .stall(stall), .clk(clk), .rst(rst)); decode.v:63:- latch en_reg_wr_latch3 (.q(en_reg_wr), .d(en_reg_wr_conn_latch2), .stall(stall), .clk(clk), .rst(rst)); decode.v:64:- decode.v:65:- latch en_jmp_latch (.q(en_jmp), .d(~squash & input_en_jmp), .stall(stall), .clk(clk), .rst(rst)); decode.v:66:- decode.v:67:- latch en_uncond_jmp_latch (.q(en_uncond_jmp), .d(~squash & input_en_uncond_jmp), .stall(stall), .clk(clk), .rst(rst)); decode.v:68:- decode.v:69:- latch en_rel_reg_jmp_latch (.q(en_rel_reg_jmp), .d(~squash &input_en_rel_reg_jmp), .stall(stall), .clk(clk), .rst(rst)); decode.v:70:- decode.v:71:- // Function code for ALU latch decode.v:72:- latch function_code_latch [9:0] (.q(func), .d({10{~squash}} & input_func), .stall(stall), .clk(clk), .rst(rst)); decode.v:73:- decode.v:74:- // Data for ALU computation latch decode.v:75:- latch data1_latch [31:0] (.q(alu_data1), .d({32{~squash}} & d0), .stall(stall), .clk(clk), .rst(rst)); decode.v:76:- latc

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: decode_logic.v:28:-`define ALU_LD 3'b001 decode_logic.v:29:-`define MEM_LD 3'b010 decode_logic.v:30:-`define IMM_LD 3'b011 decode_logic.v:31:-`define PC_LD 3'b100 decode_logic.v:32:-`define PC_PIMM_LD 3'b101 decode_logic.v:33:-`define NO_LD 3'b000 decode_logic.v:28:+`define ALU_LD 3'b001 decode_logic.v:29:+`define MEM_LD 3'b010 decode_logic.v:30:+`define IMM_LD 3'b011 decode_logic.v:31:+`define PC_LD 3'b100 decode_logic.v:32:+`define PC_PIMM_LD 3'b101 decode_logic.v:33:+`define NO_LD 3'b000

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: decode_logic.v:35:-module decode_logic(a0, a1, a2, imm, func, en_jmp, en_uncond_jmp, en_imm, en_reg_wr, en_mem_wr, en_rel_reg_jmp, ld_code, dmem_addr_bus_use, instr); decode_logic.v:36:- input [31:0] instr; decode_logic.v:37:- output reg [`REG_BITS-1:0] a0; decode_logic.v:38:- output reg [`REG_BITS-1:0] a1; decode_logic.v:39:- output reg [`REG_BITS-1:0] a2; decode_logic.v:40:- output reg [31:0] imm; decode_logic.v:41:- output reg [`FUNC1_BITS+`FUNC2_BITS-1:0] func; decode_logic.v:42:- output reg en_jmp; decode_logic.v:43:- output reg en_uncond_jmp; decode_logic.v:44:- output reg en_imm; decode_logic.v:45:- output reg en_reg_wr; decode_logic.v:46:- output reg en_mem_wr; decode_logic.v:47:- output reg en_rel_reg_jmp; decode_logic.v:48:- output reg [2:0] ld_code; decode_logic.v:49:- output reg dmem_addr_bus_use; decode_logic.v:35:+module decode_logic ( decode_logic.v:36:+ a0, decode_logic.v:37:+ a1, decode_logic.v:38:+ a2, decode_logic.v:39:+ imm, decode_logic.v:40:+ func, decode_logic.v:41:+ en_jmp, decode_logic.v:42:+ en_uncond_jmp, decode_logic.v:43:+ en_imm, decode_logic.v:44:+ en_reg_wr, decode_logic.v:45:+ en_mem_wr, decode_logic.v:46:+ en_rel_reg_jmp, decode_logic.v:47:+ ld_code, decode_logic.v:48:+ dmem_addr_bus_use, decode_logic.v:49:+ instr decode_logic.v:50:+); decode_logic.v:51:+ input [31:0] instr; decode_logic.v:52:+ output reg [`REG_BITS-1:0] a0; decode_logic.v:53:+ output reg [`REG_BITS-1:0] a1; decode_logic.v:54:+ output reg [`REG_BITS-1:0] a2; decode_logic.v:55:+ output reg [31:0] imm; decode_logic.v:56:+ output reg [`FUNC1_BITS+`FUNC2_BITS-1:0] func; decode_logic.v:57:+ output reg en_jmp; decode_logic.v:58:+ output reg en_uncond_jmp; decode_logic.v:59:+ output reg en_imm; decode_logic.v:60:+ output reg en_reg_wr; decode_logic.v:61:+ output reg en_mem_wr; decode_logic.v:62:+ output reg en_rel_reg_jmp; decode_logic.v:63:+ output reg [2:0] ld_code; decode_logic.v:64:+ output reg dmem_addr_bus_use;

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: decode_logic.v:71:- always @ (*) begin decode_logic.v:72:- case({instr[`OPCODE_SIZE-1:0]}) decode_logic.v:73:- `LOAD_UPPER_IMM: begin decode_logic.v:74:- imm_pos = `FORMAT_U; decode_logic.v:75:- ld_code = `IMM_LD; decode_logic.v:76:- en_jmp = 1'b0; decode_logic.v:77:- en_uncond_jmp = 1'b0; decode_logic.v:78:- en_rel_reg_jmp = 1'b0; decode_logic.v:79:- en_imm = 1'b0; decode_logic.v:80:- en_reg_wr = 1'b1; decode_logic.v:81:- en_mem_wr = 1'b0; decode_logic.v:82:- en_alu_str_func = 1'b0; decode_logic.v:83:- dmem_addr_bus_use = 1'b0; decode_logic.v:84:- end decode_logic.v:85:- `ADD_UPPER_IMM_PC: begin decode_logic.v:86:- imm_pos = `FORMAT_U; decode_logic.v:87:- ld_code = `PC_PIMM_LD; decode_logic.v:88:- en_jmp = 1'b0; decode_logic.v:89:- en_uncond_jmp = 1'b0; decode_logic.v:90:- en_imm = 1'b0; decode_logic.v:91:- en_reg_wr = 1'b1; decode_logic.v:92:- en_mem_wr = 1'b0; decode_logic.v:93:- en_alu_str_func = 1'b0; decode_logic.v:94:- dmem_addr_bus_use = 1'b0; decode_logic.v:95:- end decode_logic.v:96:- `JUMP_AND_LINK: begin decode_logic.v:97:- imm_pos = `FORMAT_J; decode_logic.v:98:- ld_code = `PC_LD; decode_logic.v:99:- en_jmp = 1'b1; decode_logic.v:100:- en_uncond_jmp = 1'b1; decode_logic.v:101:- en_rel_reg_jmp = 1'b0; decode_logic.v:102:- en_imm = 1'b1; decode_logic.v:103:- en_reg_wr = 1'b1; decode_logic.v:104:- en_mem_wr = 1'b0; decode_logic.v:105:- en_alu_str_func = 1'b0; decode_logic.v:106:- dmem_addr_bus_use = 1'b0; decode_logic.v:107:- end decode_logic.v:108:- `JUMP_AND_LINK_REG: begin decode_logic.v:109:- imm_pos = `FORMAT_I; decode_logic.v:110:- ld_code = `PC_LD; decode_logic.v:111:- en_jmp = 1'b1; decode_logic.v:112:- en_uncond_jmp = 1'b0; decode_logic.v:113:- en_rel_reg_jmp = 1'b1; decode_logic.v:114:- en_imm = 1'b1; decode_logic.v:115:- en_reg_wr = 1'b1; decode_logic.v:116:- en_mem_wr = 1'b0; decode_logic.v:117:- en_alu_str_func = 1'b0; decode_logic.v:118:- dmem_addr_bus_use = 1'b0; decode_logic.v:119:- end decode_logic.v:120:- `LOAD_OP: begin decode_logic.v:121:- imm_pos = `FORMAT_I; decode_logic.v:122:- ld_code = `MEM_LD; decode_logic.v:123:- en_jmp = 1'b0; decode_logic.v:124:- en_uncond_jmp = 1'b0; decode_logic.v:125:- en_rel_reg_jmp = 1'b0; decode_logic.v:126:- en_imm = 1'b1; decode_logic.v:127:- en_reg_wr = 1'b1; decode_logic.v:128:- en_mem_wr = 1'b0; decode_logic.v:129:- en_alu_str_func = 1'b1; decode_logic.v:130:- dmem_addr_bus_use = 1'b1; decode_logic.v:131:- end decode_logic.v:132:- `STORE_OP: begin decode_logic.v:133:- imm_pos = `FORMAT_S; decode_logic.v:134:- ld_code = `NO_LD; decode_logic.v:135:- en_jmp = 1'b0; decode_logic.v:136:- en_uncond_jmp = 1'b0; decode_logic.v:137:- en_rel_reg_jmp = 1'b0; decode_logic.v:138:- en_imm = 1'b1; decode_logic.v:139:- en_reg_wr = 1'b0; decode_logic.v:140:- en_mem_wr = 1'b1; decode_logic.v:141:- en_alu_str_func = 1'b1; decode_logic.v:142:- dmem_addr_bus_use = 1'b1; decode_logic.v:143:- end decode_logic.v:144:- `BRANCH_OP: begin decode_logic.v:145:- imm_pos = `FORMAT_B; deco

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: fetch.v:6:-module fetch (curr_addr, instr_out, curr_addr_step_out, curr_addr_addval_out, fetch.v:7:- instr_in, jump_taken, alu_bits, en_uncond_jmp, en_rel_reg_jmp, fetch.v:8:- en_branch, en_jmp, imm, stall, imem_stall, clk, rst); fetch.v:9:- fetch.v:10:- // Current Address fetch.v:11:- output wire [31:0] curr_addr; fetch.v:12:- // Instruction coming out of fetch stage fetch.v:13:- output wire [31:0] instr_out; fetch.v:14:- // Leaving Fetch Stage, Current address plus four bytes fetch.v:15:- output wire [31:0] curr_addr_step_out; fetch.v:16:- // Leaving Fetch Stage, Current address plus relative jump fetch.v:17:- output wire [31:0] curr_addr_addval_out; fetch.v:18:- fetch.v:19:- fetch.v:20:- // Instruction coming directly from memory fetch.v:21:- input wire [31:0] instr_in; fetch.v:22:- // From Main Processor, signal that tells whether a jump will be taken or not fetch.v:23:- input wire jump_taken; fetch.v:24:- // From Execute, the address from the ALU fetch.v:25:- input wire [31:0] alu_bits; fetch.v:26:- // From Decode, signal that enables jumps fetch.v:27:- input wire en_jmp; fetch.v:28:- // From Decode, signal that enables unconditional jumps fetch.v:29:- input wire en_uncond_jmp; fetch.v:30:- // From Decode, signal that enables jumps using a register and an immediate fetch.v:31:- input wire en_rel_reg_jmp; fetch.v:32:- // From Decode, signal that enables a branch to be taken fetch.v:33:- input wire en_branch; fetch.v:34:- // From Decode, the immediate value from the instruction fetch.v:35:- input wire [31:0] imm; fetch.v:36:- // Signal that informs whether a stall is occuring from the data cache fetch.v:37:- input wire stall; fetch.v:38:- // Signal designating if the instruction memory was successfully read from fetch.v:39:- input wire imem_stall; fetch.v:40:- // Clock and Reset fetch.v:41:- input wire clk, rst; fetch.v:42:- fetch.v:43:- fetch.v:44:- // Current Address After 4 Byte Step fetch.v:45:- wire [31:0] curr_addr_step; fetch.v:46:- // Current Address plus relative jump fetch.v:47:- wire [31:0] curr_addr_addval; fetch.v:48:- fetch.v:49:- fetch.v:50:- // Next Address to be used put onto the cache fetch.v:51:- reg [31:0] next_addr; fetch.v:52:- fetch.v:53:- // Program Counter fetch.v:54:- latch pc [31:0] (.q(curr_addr), .d(next_addr), .stall(stall | imem_stall), .clk(clk), .rst(rst)); fetch.v:55:- fetch.v:56:- // Instruction Latch fetch.v:57:- latch instr_latch [31:0] (.q(instr_out), .d(instr_in), .stall(stall), .clk(clk), .rst(rst)); fetch.v:58:- fetch.v:59:- // Latch for the current address plus four bytes fetch.v:60:- wire [31:0] curr_addr_step_conn_latch1; fetch.v:61:- wire [31:0] curr_addr_step_conn_latch2; fetch.v:62:- wire [31:0] curr_addr_step_conn_latch3; fetch.v:63:- latch curr_addr_step_latch1 [31:0] (.q(curr_addr_step_conn_latch1), .d(curr_addr_step), .stall(stall), .clk(clk), .rst(rst)); fetch.v:64:- latch curr_addr_step_latch2 [31:0] (.q(curr_addr_step_conn_latch2), .d(curr_addr_step_conn_latch1), .stall(stall), .clk(clk), .rst(rst)); fetch.v:65:- latch curr_addr_step_latch3 [31:0] (.q(curr_addr_step_conn_latch3), .d(curr_addr_step_conn_latch2), .stall(stall), .clk(clk), .rst(rst)); fetch.v:66:- latch curr_addr_step_latch4 [31:0] (.q(curr_addr_step_out), .d(curr_addr_step_conn_latch3), .stall(stall), .clk(clk), .rst(rst)); fetch.v:67:- fetch.v:68:- // Latch for the current address plus the additional value fetch.v:69:- wire [31:0] curr_addr_addval_conn_latch1; fetch.v:70:- latch curr_addr_addval_latch1 [31:0] (.q(curr_addr_addval_conn_latch1), .d(curr_addr_addval), .stall(stall), .clk(clk), .rst(rst)); fetch.v:71:- latch curr_addr_addval_latch2 [31:0] (.q(curr_addr_addval_out), .d(curr_addr_addval_conn_latch1), .stall(stall), .clk(clk), .rst(rst)); fetch.v:72:- fetch.v:73:- // Latch for current address fetch.v:74:- wire [31:0] c

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: hazards.v:11:- input wire jump_taken; hazards.v:12:- input wire dmem_ready; hazards.v:13:- input wire imem_ready; hazards.v:14:- input wire dmem_use; hazards.v:15:- input wire [4:0] a0; hazards.v:16:- input wire [4:0] a1; hazards.v:17:- input wire [4:0] a2; hazards.v:18:- input wire clk, rst; hazards.v:20:+ output wire control_hazard; hazards.v:21:+ output wire data_hazard; hazards.v:22:+ output wire dmem_stall; hazards.v:23:+ output wire imem_stall; hazards.v:24:+ output wire stall;