GitHub - isurunuwanthilaka/Image-Down-Sampling-Custom-Processor: This implementation is for down sampling a image using sparton 6 FPGA. This is a custom processor with custom ISA.

Image-Down-Sampling-Custom-Processor

This project is to down sample a 256*256 image to 128*128 image.

Here we have several process to decide before implementing the code.

Date : 2018.06.22 Project : Semester 5 group project Authers: Isuru Nuwanthilaka,Chirath Diyagama,Chandula Nethmal,Dileepa Perera

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
Algorithm		Algorithm
Codes		Codes
Compiler		Compiler
Downsample		Downsample
ALU.v		ALU.v
AR.v		AR.v
Addres_controller.v		Addres_controller.v
Baud_tick_gen.v		Baud_tick_gen.v
ClockDivider.v		ClockDivider.v
Com_controller.v		Com_controller.v
DR.v		DR.v
DRAM.v		DRAM.v
Decoder.v		Decoder.v
IR.v		IR.v
IRAM.v		IRAM.v
PC.v		PC.v
Processor.v		Processor.v
R10.v		R10.v
R11.v		R11.v
R12.v		R12.v
R13.v		R13.v
R14.v		R14.v
R15.v		R15.v
R16.v		R16.v
R17.v		R17.v
R18.v		R18.v
R19.v		R19.v
R8.v		R8.v
README.md		README.md
Ra.v		Ra.v
Rb.v		Rb.v
RegAcontroller.v		RegAcontroller.v
RegBcontroller.v		RegBcontroller.v
RegCcontroller.v		RegCcontroller.v
RegYcontroller.v		RegYcontroller.v
Ry.v		Ry.v
Top_module.v		Top_module.v
Top_module_synthesis.v		Top_module_synthesis.v
UART_Transmitter.v		UART_Transmitter.v
UART_receiver.v		UART_receiver.v
integrated_test.v		integrated_test.v
processor_test.v		processor_test.v
state_machine.v		state_machine.v
test_reg.v		test_reg.v
top_tb.v		top_tb.v