Developed Flappy Bird with SystemVerilog, ModelSIM on the Altera DE1SoC Cyclone V FPGA using ASMD and FSM design methodologies. This project was done for ECE 371 at the University of Washington. We used the mouse to control the bird and the HEX board on the FPGA to show the score.
Block Diagram for the System:
The Finite State Machine for the game manager:
Game Screenshots:
In depth analysis of the code and design methodologies are outlined in the lab report attached