Name		Name	Last commit message	Last commit date
Latest commit History 116 Commits
ALU Design		ALU Design
Adders		Adders
Alarm		Alarm
Barrel Shifter		Barrel Shifter
Button Debouncer		Button Debouncer
CEN321 Labs		CEN321 Labs
Clock Divider		Clock Divider
Combinational Logic Components		Combinational Logic Components
Counters		Counters
Digital Alarm		Digital Alarm
Digital Delay Timer		Digital Delay Timer
Division		Division
FIFO Memory		FIFO Memory
Floating Point Arithmetic		Floating Point Arithmetic
Laser Distance Measurer		Laser Distance Measurer
N-Bit Adder-Subtructer		N-Bit Adder-Subtructer
N-Bit Shifter		N-Bit Shifter
N-bit Adder		N-bit Adder
PS2KB Interface		PS2KB Interface
PWM Gen		PWM Gen
PWM Generator		PWM Generator
Park System Controller		Park System Controller
Pattern Recognition Example		Pattern Recognition Example
Shift Registers		Shift Registers
Storing Data		Storing Data
Traffic Light Controller		Traffic Light Controller
Tutorial - Level Sensitive UDPs		Tutorial - Level Sensitive UDPs
Tutorial - Reentrant Functions		Tutorial - Reentrant Functions
Tutorial - Tasks		Tutorial - Tasks
UART		UART
README.md		README.md

Repository files navigation

Verilog

For FPGA