Basic description of RISC-V32 I + M + ZIFENCEI ISA

[clebreto]

Provide:

• generalization to prepare for riscv:
  • generalize eval_cond : (rflag_t -> exec bool) -> cond_t -> exec bool so that it allows for reg arguments. #700
• ISA description (riscv_desc.v), parsing & compilation:
  • describe registers and first ADD / ADDI intructions #705
  • SUB / SUBI, AND / ANDI, MOVE (mv rd,rs addi rd,rs,0) -> print mv as pseudoinstruction, LOAD WORD (lw rd, imm(rs1)), STORE WORD (sw rs2, imm(rs1) ) #714
  • Add two more RISC-V instructions #739
  • compilation of a void function (compiler skeleton) #744
  • Make bug_499.jazz compilable for RISC-V #755
  • Condition : allow comparison between register and immediate
    • For comparison with 0
      • Use option register type to model x0 as a hack
      • Wrap get function (riscv_eval_cond)
      • Update assemble_cond
    • For comparison with any immediate not 0
      • Introduce lower_condition to handle the different possibilities
  • Let all common, namespaces/common tests pass
  • Let (some / all )ARM tests pass for risc-v (noably large-stack related tests)
    • Likely requires stack zeroization
    • RISC-V : Test every instructions in a same fashion as it was done for ARM #789
  • Implement the zeroization
  • Renames registers with their more specific naming to ease readability of assembly code
  • Allow to (optionally) execute the risc-v tests (spike or qemu)
  • Fuzzing to verify the semantics of instructions (from work done in arm and x86)
  • Optimize assembly using x0

Docs:

• riscv-spec-20191213.pdf
• a cheatsheet
• As decribed on the GCC RISC-V Options pages : General-purpose computing base extension, ‘g’ will expand to ‘i’, ‘m’, ‘a’, ‘f’, ‘d’, ‘zicsr’ and ‘zifencei’.
• Assembly and execution of risc-v assembly code generated by jasminc compiler can be easily achieved on Macos arm M1 / M2 / M3 with the homebrew precompiled binaries of riscv-tools (compiler and spike) for Sonoma : bottle

./jasminc -arch=risc-v ./tests/success/risc-v/basics.jazz -o basics.s
/opt/homebrew/bin/riscv64-unknown-elf-gcc basics -o basics
/opt/homebrew/bin/spike pk basics

To dump objdump:

/opt/homebrew/bin/riscv64-unknown-elf-objdump execution.o -D

To check if the assembly code syntaxically valid with respect to risc-v isa, use /opt/homebrew/bin/riscv64-unknown-elf-as

• On Linux
  • The compiler is https://github.com/riscv-collab/riscv-gnu-toolchain (2 hours to compile...)
  • Compile with -static
  • To run, use qemu-riscv32-static (calling normally the executable calls qemu, so you can ignore that part)