RECON 0a

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JEFF LIEU edited this page Dec 26, 2017 · 4 revisions

Features:

This architecture enhances RECON-0 architecture with an ADC sequencer.

80MHz system clock
On-chip flash to store program and fpga configuration. Program can be executed in flash.
16kB RAM for Programme and Data
4kB RAM for exceptions handlers
32 IO pins that supports PWM, Programmable Frequency, Interrupts
Timer to support delay
UART controller with configurable baudrate
ADC sequencer that reads 9 analogue pins and on chip temperature sensor diode (TSD)