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Add images for assignemnt 7
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Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
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powerjg committed Dec 31, 2024
1 parent dd5706f commit 9f2f67d
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Showing 8 changed files with 11 additions and 12 deletions.
21 changes: 10 additions & 11 deletions assignment-7/components/__init__.py
Original file line number Diff line number Diff line change
Expand Up @@ -8,25 +8,24 @@
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import ISA

from cache_hierarchies import HW5MESITwoLevelCacheHierarchy
from cache_hierarchies import MESITwoLevelCacheHierarchy

HW5RISCVBoard = SimpleBoard
X86Board = SimpleBoard


class HW5DDR4(ChanneledMemory):
class DDR4(ChanneledMemory):
"""
HW5DDR4 models a 1 GiB single channel DDR4 DRAM memory with a data
DDR4 models a 1 GiB single channel DDR4 DRAM memory with a data
bus clocked at 2400MHz.
"""

def __init__(self):
super().__init__(DDR4_2400_8x8, 1, 128, size="1GiB")


class HW5O3CPU(SimpleProcessor):
class O3CPU(SimpleProcessor):
def __init__(self, num_cores: int):
"""
HW5O3CPU is an out of order processor with a configurable number of
O3CPU is an out of order processor with a configurable number of
cores. Note that because of limitations of SE mode and OpenMP we need
to have one more core than specified. E.g., for 4 threads you need 5
cores. You should ignore the "first" core's stats.
Expand All @@ -42,8 +41,8 @@ def get_actual_num_cores(self):


__all__ = [
"HW5RISCVBoard",
"HW5DDR4",
"HW5O3CPU",
"HW5MESITwoLevelCacheHierarchy",
"X86Board",
"DDR4",
"O3CPU",
"MESITwoLevelCacheHierarchy",
]
2 changes: 1 addition & 1 deletion assignment-7/components/cache_hierarchies.py
Original file line number Diff line number Diff line change
Expand Up @@ -51,7 +51,7 @@
RubyPortProxy,
)

class HW5MESITwoLevelCacheHierarchy(
class MESITwoLevelCacheHierarchy(
AbstractRubyCacheHierarchy, AbstractTwoLevelCacheHierarchy
):
"""A two level private L1 shared L2 MESI hierarchy.
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