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The jTDC is an FPGA based high resolution TDC implemented on Xilinx Spartan 6 and compatible FPGAs. It is used at the BGO-OD experiment (↗) located at the ELSA facility (↗) in Bonn/Germany.

This repository not only contains the sources for the core modules of the jTDC, but also two complete example implementations designed for the VFB6 FPGA board (↗) manufactured by ELB (↗). I will include any other working implementation for other FPGA boards, if provided.

Furthermore, this repository contains jDaqLite, which is a reference tool to configure, monitor and read-out the jTDC. It also contains jAnalyzer, which reads data files generated by jDaqLite, extracts the actual tdc data and generates some example plots.

General features of the jTDC

• Up to 100 TDC channels per board with 40ps average bin size (30ps RMS **).
• All inputs can be inverted.
• Scalers (32bit @200MHz) for every input channel, which can also operate in duty cycle mode.
• Scalers support a lifetime-count-mode, if DAQ provides a deadtime/busy signal.
• Maximum input rate without missing hits: 200MHz ** (valid for all inputs at the same time).
• Minimum length of input signals: 3ns **
• Double pulse resolution: 5ns **
• Max hits per event stored in DATA-FIFO: 15.360, limiting the trigger window to 775ns at full rate on all channels (at lower rate limited by BRAM size to 1250ns).
• Read-out during lifetime.
• 2 Trigger outputs available (logical OR of all input signals or subsets).

** These features are limited by the hardware (Xilinx Spartan 6) and cannot be easily improved. All other limits are limits by choice (only 17% of RAM resources used, so plenty of space for more channels/larger FIFOs).