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Map Reports.txt
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Map Reports.txt
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Release 14.7 Map P.20131013 (nt64)
Xilinx Mapping Report File for Design 'Neural_net'
Design Information
------------------
Command Line : map -intstyle ise -p xc7a100t-csg324-3 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -mt off -ir off -pr off -lc off
-power off -o Neural_net_map.ncd Neural_net.ngd Neural_net.pcf
Target Device : xc7a100t
Target Package : csg324
Target Speed : -3
Mapper Version : artix7 -- $Revision: 1.55 $
Mapped Date : Tue Sep 13 18:46:22 2022
Interim Summary
---------------
Slice Logic Utilization:
Number of Slice Registers: 1,737 out of 126,800 1%
Number used as Flip Flops: 0
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 1,737
Number of Slice LUTs: 7,988 out of 63,400 12%
Number used as logic: 7,932 out of 63,400 12%
Number using O6 output only: 5,155
Number using O5 output only: 742
Number using O5 and O6: 2,035
Number used as ROM: 0
Number used as Memory: 0 out of 19,000 0%
Number used exclusively as route-thrus: 56
Number with same-slice register load: 0
Number with same-slice carry load: 56
Number with other load: 0
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 7,988
Number with an unused Flip Flop: 6,251 out of 7,988 78%
Number with an unused LUT: 0 out of 7,988 0%
Number of fully used LUT-FF pairs: 1,737 out of 7,988 21%
Number of slice register sites lost
to control set restrictions: 0 out of 126,800 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
OVERMAPPING of BRAM resources should be ignored if the design is
over-mapped for a non-BRAM resource or if placement fails.
IO Utilization:
Number of bonded IOBs: 994 out of 210 473% (OVERMAPPED)
Specific Feature Utilization:
Number of RAMB36E1/FIFO36E1s: 0 out of 135 0%
Number of RAMB18E1/FIFO18E1s: 0 out of 270 0%
Number of BUFG/BUFGCTRLs: 0 out of 32 0%
Number of IDELAYE2/IDELAYE2_FINEDELAYs: 0 out of 300 0%
Number of ILOGICE2/ILOGICE3/ISERDESE2s: 0 out of 300 0%
Number of ODELAYE2/ODELAYE2_FINEDELAYs: 0
Number of OLOGICE2/OLOGICE3/OSERDESE2s: 0 out of 300 0%
Number of PHASER_IN/PHASER_IN_PHYs: 0 out of 24 0%
Number of PHASER_OUT/PHASER_OUT_PHYs: 0 out of 24 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHCEs: 0 out of 96 0%
Number of BUFRs: 0 out of 24 0%
Number of CAPTUREs: 0 out of 1 0%
Number of DNA_PORTs: 0 out of 1 0%
Number of DSP48E1s: 240 out of 240 100%
Number of EFUSE_USRs: 0 out of 1 0%
Number of FRAME_ECCs: 0 out of 1 0%
Number of IBUFDS_GTE2s: 0 out of 4 0%
Number of ICAPs: 0 out of 2 0%
Number of IDELAYCTRLs: 0 out of 6 0%
Number of IN_FIFOs: 0 out of 24 0%
Number of MMCME2_ADVs: 0 out of 6 0%
Number of OUT_FIFOs: 0 out of 24 0%
Number of PCIE_2_1s: 0 out of 1 0%
Number of PHASER_REFs: 0 out of 6 0%
Number of PHY_CONTROLs: 0 out of 6 0%
Number of PLLE2_ADVs: 0 out of 6 0%
Number of STARTUPs: 0 out of 1 0%
Number of XADCs: 0 out of 1 0%
Mapping completed.
See MAP report file "Neural_net_map.mrp" for details.
Problem encountered during the packing phase.
Design Summary
--------------
Number of errors : 2
Number of warnings : 2
Section 1 - Errors
------------------
ERROR:Pack:2309 - Too many bonded comps of type "IOB" found to fit this device.
ERROR:Map:237 - The design is too large to fit the device. Please check the Design Summary section to see which resource requirement for
your design exceeds the resources available in the device. Note that the number of slices reported may not be reflected accurately as
their packing might not have been completed.
Section 2 - Warnings
--------------------
WARNING:LIT:701 - PAD symbol "uzorak<959>" has an undefined IOSTANDARD.
WARNING:LIT:702 - PAD symbol "uzorak<959>" is not constrained (LOC) to a
specific location.
Section 3 - Informational
-------------------------
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 0.950 Volts. (default - Range: 0.950 to
1.050 Volts)
Section 4 - Removed Logic Summary
---------------------------------
22 block(s) removed
110 block(s) optimized away
Section 5 - Removed Logic
-------------------------
The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections. If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented. This
indentation will be repeated as a chain of related logic is removed.
To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).
Loadless block "ADDERTREE_INTERNAL_Madd10321" (ROM) removed.
Loadless block "ADDERTREE_INTERNAL_Madd11421" (ROM) removed.
Loadless block "ADDERTREE_INTERNAL_Madd13021" (ROM) removed.
Loadless block "ADDERTREE_INTERNAL_Madd1428" (ROM) removed.
Loadless block "ADDERTREE_INTERNAL_Madd14521" (ROM) removed.
Loadless block "ADDERTREE_INTERNAL_Madd15921" (ROM) removed.
Loadless block "ADDERTREE_INTERNAL_Madd17225" (ROM) removed.
Loadless block "ADDERTREE_INTERNAL_Madd18921" (ROM) removed.
Loadless block "ADDERTREE_INTERNAL_Madd20521" (ROM) removed.
Loadless block "ADDERTREE_INTERNAL_Madd21821" (ROM) removed.
Loadless block "ADDERTREE_INTERNAL_Madd23021" (ROM) removed.
Loadless block "ADDERTREE_INTERNAL_Madd24721" (ROM) removed.
Loadless block "ADDERTREE_INTERNAL_Madd26321" (ROM) removed.
Loadless block "ADDERTREE_INTERNAL_Madd27621" (ROM) removed.
Loadless block "ADDERTREE_INTERNAL_Madd28821" (ROM) removed.
Loadless block "ADDERTREE_INTERNAL_Madd2947" (ROM) removed.
Loadless block "ADDERTREE_INTERNAL_Madd4321" (ROM) removed.
Loadless block "ADDERTREE_INTERNAL_Madd5621" (ROM) removed.
Loadless block "ADDERTREE_INTERNAL_Madd7421" (ROM) removed.
Loadless block "ADDERTREE_INTERNAL_Madd9130" (ROM) removed.
Loadless block "prvi_neuron_prvi_sloj/Msub_GND_2_o_N_suma[27][21]_sub_123_OUT21"
(ROM) removed.
Loadless block "prvi_neuron_prvi_sloj/Msub_GND_2_o_P_suma[31][21]_sub_125_OUT21"
(ROM) removed.
Optimized Block(s):
TYPE BLOCK
LUT3 ADDERTREE_INTERNAL_Madd10318
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd10319
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd10320
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd103_lut<0>19
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd103_lut<0>20
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd103_lut<0>21
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd11418
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd11419
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd11420
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd114_lut<0>19
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd114_lut<0>20
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd114_lut<0>21
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd13018
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd13019
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd13020
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd130_lut<0>19
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd130_lut<0>20
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd130_lut<0>21
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd1425
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd1426
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd1427
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd14518
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd14519
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd14520
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd145_lut<0>19
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd145_lut<0>20
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd145_lut<0>21
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd14_lut<0>19
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd14_lut<0>20
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd14_lut<0>21
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd15918
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd15919
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd15920
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd159_lut<0>19
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd159_lut<0>20
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd159_lut<0>21
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd17222
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd17223
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd17224
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd172_lut<0>19
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd172_lut<0>20
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd172_lut<0>21
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd18919
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd18920
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd189_lut<0>20
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd189_lut<0>21
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd20519
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd20520
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd205_lut<0>20
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd205_lut<0>21
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd21818
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd21819
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd21820
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd218_lut<0>19
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd218_lut<0>20
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd218_lut<0>21
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd23018
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd23019
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd23020
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd230_lut<0>19
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd230_lut<0>20
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd230_lut<0>21
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd24719
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd24720
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd247_lut<0>20
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd247_lut<0>21
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd26319
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd26320
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd263_lut<0>20
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd263_lut<0>21
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd27618
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd27619
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd27620
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd276_lut<0>19
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd276_lut<0>20
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd276_lut<0>21
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd28818
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd28819
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd28820
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd288_lut<0>19
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd288_lut<0>20
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd288_lut<0>21
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd2944
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd2945
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd2946
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd29_lut<0>19
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd29_lut<0>20
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd29_lut<0>21
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd4318
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd4319
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd4320
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd43_lut<0>19
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd43_lut<0>20
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd43_lut<0>21
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd5618
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd5619
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd5620
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd56_lut<0>19
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd56_lut<0>20
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd56_lut<0>21
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd7419
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd7420
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd74_lut<0>20
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd74_lut<0>21
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd9128
optimized to 0
LUT3 ADDERTREE_INTERNAL_Madd9129
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd91_lut<0>20
optimized to 0
LUT4 ADDERTREE_INTERNAL_Madd91_lut<0>21
optimized to 0
GND XST_GND
VCC XST_VCC
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 12 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 13 - Control Set Information
------------------------------------
Use the "-detail" map option to print out Control Set Information.