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Conception d'un processeur RISC-V et implémentation de ses instructions et familles d'instructions typiques (VHDL & Assembleur RISC-V).

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Conception et Exploitation des Processeurs (CEP)

Instruction Status

Métadonnées

timestamp status

Fichier de log

Arithmetiques

ADDI status ADD status SUB status

Basiques

REBOUCLAGE status LUI status

Divers

AUIPC status

Logiques

OR status ORI status AND status ANDI status XOR status XORI status

Décalages

SLL status SLLI status SRA status SRAI status SRL status SRLI status

Sets

SLT status SLTI status SLTIU status SLTU status

Branchements

BEQ status BGE status BGEU status BLT status BLTU status BNE status

Sauts

JAL status JALR status

Loads

LB status LBU status LH status LHU status LW status

Stores

SB status SH status SW status

Interruptions

CSRRC status CSRRCI status CSRRS status CSRRSI status CSRRW status CSRRWI status IT status

Note

Travail effectué : toutes les instructions typiques et leur famille correspondante (tableau 2.1.2)

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Conception d'un processeur RISC-V et implémentation de ses instructions et familles d'instructions typiques (VHDL & Assembleur RISC-V).

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cep processor assembly vhdl riscv risc risc-v

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