Initial release

kelu124 · Feb 14, 2021 · c4ade4e · c4ade4e
1 parent 09a0af5
commit c4ade4e
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Showing 253 changed files with 23,133 additions and 0 deletions.
diff --git a/altium/BOM_ft600.xls b/altium/BOM_ft600.xls
diff --git a/altium/CAMtastic6.Cam b/altium/CAMtastic6.Cam
diff --git a/altium/CAMtastic7.Cam b/altium/CAMtastic7.Cam
diff --git a/altium/CAMtastic8.Cam b/altium/CAMtastic8.Cam
diff --git a/altium/History/ft600.~(1).PcbDoc.Zip b/altium/History/ft600.~(1).PcbDoc.Zip
diff --git a/altium/History/ft600.~(1).PrjPcb.Zip b/altium/History/ft600.~(1).PrjPcb.Zip
diff --git a/altium/History/ft600.~(1).SchDoc.Zip b/altium/History/ft600.~(1).SchDoc.Zip
diff --git a/altium/History/ft600.~(10).PcbDoc.Zip b/altium/History/ft600.~(10).PcbDoc.Zip
diff --git a/altium/History/ft600.~(10).SchDoc.Zip b/altium/History/ft600.~(10).SchDoc.Zip
diff --git a/altium/History/ft600.~(11).PcbDoc.Zip b/altium/History/ft600.~(11).PcbDoc.Zip
diff --git a/altium/History/ft600.~(11).SchDoc.Zip b/altium/History/ft600.~(11).SchDoc.Zip
diff --git a/altium/History/ft600.~(12).PcbDoc.Zip b/altium/History/ft600.~(12).PcbDoc.Zip
diff --git a/altium/History/ft600.~(12).SchDoc.Zip b/altium/History/ft600.~(12).SchDoc.Zip
diff --git a/altium/History/ft600.~(13).PcbDoc.Zip b/altium/History/ft600.~(13).PcbDoc.Zip
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diff --git a/altium/History/ft600.~(20).PcbDoc.Zip b/altium/History/ft600.~(20).PcbDoc.Zip
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diff --git a/altium/History/ft600.~(4).PcbDoc.Zip b/altium/History/ft600.~(4).PcbDoc.Zip
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diff --git a/altium/History/ft600.~(4).SchDoc.Zip b/altium/History/ft600.~(4).SchDoc.Zip
diff --git a/altium/History/ft600.~(40).PcbDoc.Zip b/altium/History/ft600.~(40).PcbDoc.Zip
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diff --git a/altium/Project Logs for ft600/ft600 PCB ECO 12.02.2021 11-04-06.LOG b/altium/Project Logs for ft600/ft600 PCB ECO 12.02.2021 11-04-06.LOG
diff --git a/altium/Project Logs for ft600/ft600 PCB ECO 12.02.2021 11-07-23.LOG b/altium/Project Logs for ft600/ft600 PCB ECO 12.02.2021 11-07-23.LOG
diff --git a/altium/Project Logs for ft600/ft600 PCB ECO 12.02.2021 11-18-30.LOG b/altium/Project Logs for ft600/ft600 PCB ECO 12.02.2021 11-18-30.LOG
diff --git a/altium/Project Logs for ft600/ft600 PCB ECO 12.02.2021 11-54-17.LOG b/altium/Project Logs for ft600/ft600 PCB ECO 12.02.2021 11-54-17.LOG
diff --git a/altium/Project Logs for ft600/ft600 PCB ECO 12.02.2021 11-58-17.LOG b/altium/Project Logs for ft600/ft600 PCB ECO 12.02.2021 11-58-17.LOG
@@ -0,0 +1,24 @@
+Added Component: Designator=L1(SM0603_3D_res)
+Add component (AddParameter): Name = "Author"; Value = "S. Jafar"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Case"; Value = "0805"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Component Type"; Value = "Standard"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "ComponentHeight"; Value = "1.05mm"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "CreateDate"; Value = "12/21/2015"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "LatestRevisionDate"; Value = "12/21/2015"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Manufacturer"; Value = "MURATA"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Manufacturer Part Number"; Value = "BLM21BB750SN1D"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Mounted"; Value = "Yes"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Part Description"; Value = "SMD EMIFIL Suppression Chip Ferrite Bead"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Part Number"; Value = "IND0805_MURATA_BLM21BB750SN1D"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Pin Count"; Value = "2"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Power"; Value = "700mA"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Resistance"; Value = "0.16R"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "SMD"; Value = "Yes"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Socket"; Value = "No"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Status"; Value = "None"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Table"; Value = "Inductors SMD"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Tolerance"; Value = "�25%"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Value"; Value = "75R@100MHz"; VariantName = "[No Variations]"
+Added Pin To Net: NetName=VB Pin=L1-1
+Added Pin To Net: NetName=NetC3_1 Pin=L1-2
+Added Member To Class: ClassName=ft600 Member=Component L1 75R@100MHz
diff --git a/altium/Project Logs for ft600/ft600 PCB ECO 12.02.2021 20-05-26.LOG b/altium/Project Logs for ft600/ft600 PCB ECO 12.02.2021 20-05-26.LOG
@@ -0,0 +1,7 @@
+Removed Pin From Net: NetName=rd Pin=K2-2
+Removed Pin From Net: NetName=be1 Pin=K2-4
+Removed Pin From Net: NetName=txe Pin=K2-7
+Removed Pin From Net: NetName=be0 Pin=K2-10
+Added Pin To Net: NetName=be1 Pin=K2-2
+Added Pin To Net: NetName=be0 Pin=K2-7
+Added Pin To Net: NetName=txe Pin=K2-10
diff --git a/altium/Project Logs for ft600/ft600 PCB ECO 12.02.2021 20-07-17.LOG b/altium/Project Logs for ft600/ft600 PCB ECO 12.02.2021 20-07-17.LOG
@@ -0,0 +1,7 @@
+Removed Pin From Net: NetName=oe Pin=K2-3
+Removed Pin From Net: NetName=rxf Pin=K2-8
+Removed Pin From Net: NetName=txe Pin=K2-10
+Added Pin To Net: NetName=rxf Pin=K2-3
+Added Pin To Net: NetName=rd Pin=K2-4
+Added Pin To Net: NetName=txe Pin=K2-8
+Added Pin To Net: NetName=oe Pin=K2-10
diff --git a/altium/Project Logs for ft600/ft600 PCB ECO 12.02.2021 20-34-11.LOG b/altium/Project Logs for ft600/ft600 PCB ECO 12.02.2021 20-34-11.LOG
@@ -0,0 +1 @@
+Added Class: Name=data
diff --git a/altium/Project Logs for ft600/ft600 PCB ECO 13.02.2021 17-24-20.LOG b/altium/Project Logs for ft600/ft600 PCB ECO 13.02.2021 17-24-20.LOG
@@ -0,0 +1,21 @@
+Removed Pin From Net: NetName=+3.3V Pin=K1-6
+Removed Pin From Net: NetName=+3.3V Pin=K1-12
+Removed Pin From Net: NetName=+3.3V Pin=K2-6
+Removed Pin From Net: NetName=+3.3V Pin=K2-12
+Change Component Comment : Designator=R6 Old Comment=4k7 New Comment=1.6k 1%
+Change Component Comment : Designator=R9 Old Comment=4k7 New Comment=2k
+Change Component Comment : Designator=R10 Old Comment=4k7 New Comment=2k
+Change Component Comment : Designator=R1 Old Comment=4k7 New Comment=10k
+Change Component Comment : Designator=R3 Old Comment=4k7 New Comment=10k
+Change Component Comment : Designator=R4 Old Comment=4k7 New Comment=36k
+Change Component Comment : Designator=R5 Old Comment=4k7 New Comment=36k
+Added Component: Designator=JP3(JUMPER2)
+Add component (AddParameter): Name = "Value"; Value = ""; VariantName = "[No Variations]"
+Added Pin To Net: NetName=+3.3V Pin=JP3-2
+Added Pin To Net: NetName=Vcc Pin=JP3-1
+Added Pin To Net: NetName=Vcc Pin=K1-6
+Added Pin To Net: NetName=Vcc Pin=K1-12
+Added Pin To Net: NetName=Vcc Pin=K2-6
+Added Pin To Net: NetName=Vcc Pin=K2-12
+Added Net: Name=Vcc
+Added Member To Class: ClassName=ft600 Member=Component JP3 JUMPER2
diff --git a/altium/Project Logs for ft600/ft600 SCH ECO 09.02.2021 18-50-26.LOG b/altium/Project Logs for ft600/ft600 SCH ECO 09.02.2021 18-50-26.LOG
@@ -0,0 +1,30 @@
+Change Component Designator: Old Designator=C? New Designator=C1
+Change Component Designator: Old Designator=C? New Designator=C2
+Change Component Designator: Old Designator=C? New Designator=C3
+Change Component Designator: Old Designator=C? New Designator=C4
+Change Component Designator: Old Designator=C? New Designator=C5
+Change Component Designator: Old Designator=C? New Designator=C6
+Change Component Designator: Old Designator=C? New Designator=C7
+Change Component Designator: Old Designator=C? New Designator=C8
+Change Component Designator: Old Designator=C? New Designator=C9
+Change Component Designator: Old Designator=C? New Designator=C10
+Change Component Designator: Old Designator=C? New Designator=C11
+Change Component Designator: Old Designator=IC? New Designator=IC1
+Change Component Designator: Old Designator=J? New Designator=J1
+Change Component Designator: Old Designator=JP? New Designator=JP1
+Change Component Designator: Old Designator=JP? New Designator=JP2
+Change Component Designator: Old Designator=K? New Designator=K1
+Change Component Designator: Old Designator=K? New Designator=K2
+Change Component Designator: Old Designator=L? New Designator=L1
+Change Component Designator: Old Designator=R? New Designator=R1
+Change Component Designator: Old Designator=R? New Designator=R2
+Change Component Designator: Old Designator=R? New Designator=R3
+Change Component Designator: Old Designator=R? New Designator=R4
+Change Component Designator: Old Designator=R? New Designator=R5
+Change Component Designator: Old Designator=R? New Designator=R6
+Change Component Designator: Old Designator=R? New Designator=R7
+Change Component Designator: Old Designator=R? New Designator=R8
+Change Component Designator: Old Designator=R? New Designator=R9
+Change Component Designator: Old Designator=R? New Designator=R10
+Change Component Designator: Old Designator=U? New Designator=U1
+Change Component Designator: Old Designator=Y? New Designator=Y1
diff --git a/altium/Project Logs for ft600/ft600 SCH ECO 10.02.2021 09-37-09.LOG b/altium/Project Logs for ft600/ft600 SCH ECO 10.02.2021 09-37-09.LOG
@@ -0,0 +1,4 @@
+Change Component Designator: Old Designator=C? New Designator=C12
+Change Component Designator: Old Designator=C? New Designator=C13
+Change Component Designator: Old Designator=C? New Designator=C14
+Change Component Designator: Old Designator=C? New Designator=C15
diff --git a/altium/Project Outputs for ft600/Design Rule Check - ft600.drc b/altium/Project Outputs for ft600/Design Rule Check - ft600.drc
@@ -0,0 +1,51 @@
+Protel Design System Design Rule Check
+PCB File : E:\my_work\Luc\ft600\ft600\ft600.PcbDoc
+Date     : 13.02.2021
+Time     : 17:36:22
+
+Processing Rule : Clearance Constraint (Gap=4mil) (All),(All)
+Rule Violations :0
+
+Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
+Rule Violations :0
+
+Processing Rule : Un-Routed Net Constraint ( (All) )
+Rule Violations :0
+
+Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
+Rule Violations :0
+
+Processing Rule : Width Constraint (Min=8mil) (Max=50mil) (Preferred=10mil) (All)
+Rule Violations :0
+
+Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)
+Rule Violations :0
+
+Processing Rule : Hole Size Constraint (Min=1mil) (Max=200mil) (All)
+Rule Violations :0
+
+Processing Rule : Hole To Hole Clearance (Gap=10mil) (All),(All)
+Rule Violations :0
+
+Processing Rule : Minimum Solder Mask Sliver (Gap=0mil) (All),(All)
+Rule Violations :0
+
+Processing Rule : Silk To Solder Mask (Clearance=4mil) (IsPad),(All)
+Rule Violations :0
+
+Processing Rule : Silk to Silk (Clearance=7mil) (All),(All)
+Rule Violations :0
+
+Processing Rule : Net Antennae (Tolerance=0mil) (All)
+Rule Violations :0
+
+Processing Rule : Matched Lengths(Tolerance=10mil) (InNetClass('data'))
+Rule Violations :0
+
+Processing Rule : Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
+Rule Violations :0
+
+
+Violations Detected : 0
+Waived Violations : 0
+Time Elapsed        : 00:00:02