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ๆๆฏ็่ช๏ผไบค้ๅคงๅญธ็ ็ฉถ็๏ผๆ็ๅฐ้ทๆฏๆธไฝ้ป่ทฏ่จญ่จ๏ผๅ ทๅ้ซ็็ทดๅบฆ็ Verilog ่ Python ใ
็ฎๅ้ๆบไบไธไบๅฐๆกไฝ็บๅญธ็ฟๆธไฝ้ป่ทฏ็ๅ้ก๏ผไปฅไธๆฏๆ่ช่ฑช็ไฝๅ๏ผ
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SOC: FSIC Design
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Memory controller: SDRAM controller
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ML Accelerator: 4x4 TPU, Bit-serial-CIM-Convolution-IP
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FPGA: AAML final proj