A2K-CPU

A2K is a 32-bit single cycle RISC CPU based on Harvard architecture with no cache or pipeline, by having very simple and reduced instruction set it can be used for educational purpose.

Architecture

Inspired by the MIPS and Dosage CPU, it has 16 instructions and 32 registers. Its general architecture looks like a MIPS unicycle.

Instruction Set Architecture

The A2K's instructions follows the format below:

    OpCode             Rs               Rt               Rd              Func               Cnst
/-----------\      /---------\      /---------\      /---------\      /---------\      /------------\  - R-type instruction
 0 0 0 0 0 0        0 0 0 0 0        0 0 0 0 0        0 0 0 0 0        0 0 0 0 0        0 0 0 0 0 0

and

    OpCode             Rs               Rt                             Imm
/-----------\      /---------\      /---------\          /-------------------------------\          - I-type instruction
 0 0 0 0 0 0        0 0 0 0 0        0 0 0 0 0            0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 

and

    OpCode                  Cnst                                Address
/-----------\       /-------------------\       /---------------------------------------\          - J-type instruction
 0 0 0 0 0 0         0 0 0 0 0 0 0 0 0 0         0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

The following table shows all instructions:

R-type

Instruction	Op Code	Func
add	0 0 0 0 0 0	1 1 1 1 1
sub	0 0 0 0 0 1	1 1 1 1 0
and	0 0 0 0 1 0	1 1 1 0 1
or	0 0 0 0 1 1	1 1 1 0 0
nor	0 0 0 1 0 0	1 1 0 1 1
xor	0 0 0 1 0 1	1 1 0 1 0
slt	0 0 1 0 0 0	1 1 0 0 0
seq	0 0 1 0 0 1	1 0 0 0 0

I-type

Instruction	Op Code
addi	1 0 0 0 0 0
lw	1 0 0 0 0 1
sw	1 0 0 0 1 0
andi	1 0 0 0 1 1
ori	1 0 0 1 0 0
beq	1 0 0 1 0 1
bne	1 0 0 1 1 0

J-type

Instruction	Op Code
j	1 1 1 1 1 1

Assembler

Also, this project includes an assembler which is in Phase_2/Assembler.

Hardware Description

A2K's hardware is descripted in Verilog which is added in Phase_2/Verilog

Collaborators: Alireza Tabatabaei, Adrina Ebrahimi, and Kian Majlessi