Detect AVX512 Half-precision floating point (FP16) (#83)

AVX512 FP16 instructions are supported when CPUID.(EAX=7,ECX=0):EDX[bit 23] is present. Signed-off-by: Mikko Ylinen <mikko.ylinen@intel.com>
klauspost · Jul 30, 2021 · 6903d40 · 6903d40
1 parent 8b74771
commit 6903d40
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diff --git a/cpuid.go b/cpuid.go
@@ -83,6 +83,7 @@ const (
 	AVX512DQ                            // AVX-512 Doubleword and Quadword Instructions
 	AVX512ER                            // AVX-512 Exponential and Reciprocal Instructions
 	AVX512F                             // AVX-512 Foundation
+	AVX512FP16                          // AVX-512 FP16 Instructions
 	AVX512IFMA                          // AVX-512 Integer Fused Multiply-Add Instructions
 	AVX512PF                            // AVX-512 Prefetch Instructions
 	AVX512VBMI                          // AVX-512 Vector Bit Manipulation Instructions
@@ -980,6 +981,7 @@ func support() flagSet {
 				// edx
 				fs.setIf(edx&(1<<8) != 0, AVX512VP2INTERSECT)
 				fs.setIf(edx&(1<<22) != 0, AMXBF16)
+				fs.setIf(edx&(1<<23) != 0, AVX512FP16)
 				fs.setIf(edx&(1<<24) != 0, AMXTILE)
 				fs.setIf(edx&(1<<25) != 0, AMXINT8)
 				// eax1 = CPUID.(EAX=7, ECX=1).EAX

diff --git a/featureid_string.go b/featureid_string.go