Skip to content

Commit

Permalink
sapemu: Implement other bit branching instructions
Browse files Browse the repository at this point in the history 
115/256, includes some arithmetic overflow fixes.
  • Loading branch information
@kleinesfilmroellchen
kleinesfilmroellchen committed Sep 13, 2024
1 parent 9ddb2c0 commit 3bd1d98
Show file tree
Hide file tree
Showing 2 changed files with 41 additions and 22 deletions.
9 changes: 7 additions & 2 deletions sapemu/src/smp.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -377,7 +377,12 @@ impl Smp {
// Fetch next instruction
if self.instruction_cycle == 0 {
self.current_opcode = self.read_next_pc(memory);
trace!("(@{}) fetch instruction [{:04x}] = {:02x}", self.cycle_counter, self.pc - 1, self.current_opcode);
trace!(
"(@{}) fetch instruction [{:04x}] = {:02x}",
self.cycle_counter,
self.pc.wrapping_sub(1),
self.current_opcode
);
}

// Execute tick
Expand Down Expand Up @@ -484,7 +489,7 @@ impl Smp {
/// Reads memory at the current program counter and advances it afterwards.
fn read_next_pc(&mut self, memory: &Memory) -> u8 {
let data = self.read(self.pc, memory);
self.pc += 1;
self.pc = self.pc.wrapping_add(1);
data
}

Expand Down
54 changes: 34 additions & 20 deletions sapemu/src/smp/ops.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -360,7 +360,7 @@ pub const OPCODE_TABLE: [InstructionImpl; 256] = [
macro_rules! debug_instruction {
($assembly:expr, $cycle:expr, $cpu:expr) => {
if $cycle == 0 {
log::debug!(concat!("[{:04x}] ", $assembly), $cpu.pc - 1);
log::debug!(concat!("[{:04x}] ", $assembly), $cpu.pc.wrapping_sub(1));
}
};
}
Expand Down Expand Up @@ -488,7 +488,8 @@ fn clr1_0(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionIn
set_clear_dp::<0, false>(cpu, memory, cycle, state)
}
fn bbc_0(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
todo!()
debug_instruction!("bbc 0", cycle, cpu);
branch_on_bit::<0, false>(cpu, memory, cycle, state)
}
fn or_a_dp_x(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
todo!()
Expand Down Expand Up @@ -580,7 +581,8 @@ fn set1_1(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionIn
set_clear_dp::<1, true>(cpu, memory, cycle, state)
}
fn bbs_1(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
todo!()
debug_instruction!("bbs 1", cycle, cpu);
branch_on_bit::<1, true>(cpu, memory, cycle, state)
}
fn and_a_dp(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
debug_instruction!("and a, (dp)", cycle, cpu);
Expand Down Expand Up @@ -671,7 +673,8 @@ fn clr1_1(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionIn
set_clear_dp::<1, false>(cpu, memory, cycle, state)
}
fn bbc_1(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
todo!()
debug_instruction!("bbc 1", cycle, cpu);
branch_on_bit::<1, false>(cpu, memory, cycle, state)
}
fn and_a_dp_x(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
todo!()
Expand Down Expand Up @@ -711,6 +714,7 @@ fn rol_a(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInt
todo!()
}
fn inc_x(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
debug_instruction!("inc x", cycle, cpu);
inc_register::<{ Register::X }>(cpu, cycle)
}
fn cmp_x_dp(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
Expand All @@ -732,7 +736,8 @@ fn set1_2(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionIn
set_clear_dp::<2, true>(cpu, memory, cycle, state)
}
fn bbs_2(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
todo!()
debug_instruction!("bbs 2", cycle, cpu);
branch_on_bit::<2, true>(cpu, memory, cycle, state)
}
fn eor_a_dp(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
debug_instruction!("eor a, (dp)", cycle, cpu);
Expand Down Expand Up @@ -785,7 +790,8 @@ fn push_x(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionIn
push::<{ Register::X }>(cpu, memory, cycle, state)
}
fn tclr1(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
todo!()
debug_instruction!("tclr1 addr", cycle, cpu);
test1(cpu, memory, cycle, state, |value, a| value & !a)
}
fn pcall(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
todo!()
Expand All @@ -804,7 +810,8 @@ fn clr1_2(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionIn
set_clear_dp::<2, false>(cpu, memory, cycle, state)
}
fn bbc_2(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
todo!()
debug_instruction!("bbc 2", cycle, cpu);
branch_on_bit::<2, false>(cpu, memory, cycle, state)
}
fn eor_a_dp_x(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
todo!()
Expand Down Expand Up @@ -875,7 +882,8 @@ fn set1_3(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionIn
set_clear_dp::<3, true>(cpu, memory, cycle, state)
}
fn bbs_3(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
todo!()
debug_instruction!("bbs 3", cycle, cpu);
branch_on_bit::<3, true>(cpu, memory, cycle, state)
}
fn cmp_a_dp(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
todo!()
Expand Down Expand Up @@ -941,7 +949,8 @@ fn clr1_3(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionIn
set_clear_dp::<3, false>(cpu, memory, cycle, state)
}
fn bbc_3(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
todo!()
debug_instruction!("bbc 3", cycle, cpu);
branch_on_bit::<3, false>(cpu, memory, cycle, state)
}
fn cmp_a_dp_x(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
todo!()
Expand Down Expand Up @@ -1028,7 +1037,8 @@ fn set1_4(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionIn
set_clear_dp::<4, true>(cpu, memory, cycle, state)
}
fn bbs_4(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
todo!()
debug_instruction!("bbs 4", cycle, cpu);
branch_on_bit::<4, true>(cpu, memory, cycle, state)
}
fn adc_a_dp(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
todo!()
Expand Down Expand Up @@ -1113,7 +1123,8 @@ fn clr1_4(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionIn
set_clear_dp::<4, false>(cpu, memory, cycle, state)
}
fn bbc_4(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
todo!()
debug_instruction!("bbc 4", cycle, cpu);
branch_on_bit::<4, false>(cpu, memory, cycle, state)
}
fn adc_a_dp_x(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
todo!()
Expand Down Expand Up @@ -1151,7 +1162,6 @@ fn dec_dp_x(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: Instruction
}
fn dec_a(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
debug_instruction!("dec a", cycle, cpu);

dec_register::<{ Register::A }>(cpu, cycle)
}
fn mov_x_sp(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
Expand All @@ -1176,7 +1186,8 @@ fn set1_5(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionIn
set_clear_dp::<5, true>(cpu, memory, cycle, state)
}
fn bbs_5(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
todo!()
debug_instruction!("bbs 5", cycle, cpu);
branch_on_bit::<5, true>(cpu, memory, cycle, state)
}
fn sbc_a_dp(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
todo!()
Expand Down Expand Up @@ -1277,7 +1288,8 @@ fn clr1_5(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionIn
set_clear_dp::<5, false>(cpu, memory, cycle, state)
}
fn bbc_5(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
todo!()
debug_instruction!("bbc 5", cycle, cpu);
branch_on_bit::<5, false>(cpu, memory, cycle, state)
}
fn sbc_a_dp_x(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
todo!()
Expand Down Expand Up @@ -1382,7 +1394,8 @@ fn set1_6(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionIn
set_clear_dp::<6, true>(cpu, memory, cycle, state)
}
fn bbs_6(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
todo!()
debug_instruction!("bbs 6", cycle, cpu);
branch_on_bit::<6, true>(cpu, memory, cycle, state)
}
fn mov_dp_a(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
debug_instruction!("mov dp, a", cycle, cpu);
Expand Down Expand Up @@ -1467,7 +1480,8 @@ fn clr1_6(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionIn
set_clear_dp::<6, false>(cpu, memory, cycle, state)
}
fn bbc_6(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
todo!()
debug_instruction!("bbc 6", cycle, cpu);
branch_on_bit::<6, false>(cpu, memory, cycle, state)
}
fn mov_dp_x_a(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
debug_instruction!("mov dp+x, a", cycle, cpu);
Expand Down Expand Up @@ -1531,7 +1545,6 @@ fn mov_dp_indirect_y_a(
}
fn mov_dp_x(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
debug_instruction!("mov dp, x", cycle, cpu);

move_to_dp::<{ Register::X }>(cpu, memory, cycle, state)
}
fn mov_dp_y_x(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
Expand Down Expand Up @@ -1573,7 +1586,6 @@ fn mov_dp_x_y(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: Instructi
}
fn dec_y(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
debug_instruction!("dec y", cycle, cpu);

dec_register::<{ Register::Y }>(cpu, cycle)
}
fn mov_a_y(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
Expand Down Expand Up @@ -1608,7 +1620,8 @@ fn set1_7(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionIn
set_clear_dp::<7, true>(cpu, memory, cycle, state)
}
fn bbs_7(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
todo!()
debug_instruction!("bbs 7", cycle, cpu);
branch_on_bit::<7, true>(cpu, memory, cycle, state)
}
fn mov_a_dp(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
debug_instruction!("mov a, dp", cycle, cpu);
Expand Down Expand Up @@ -1675,7 +1688,8 @@ fn clr1_7(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionIn
set_clear_dp::<7, false>(cpu, memory, cycle, state)
}
fn bbc_7(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
todo!()
debug_instruction!("bbc 7", cycle, cpu);
branch_on_bit::<7, false>(cpu, memory, cycle, state)
}
fn mov_a_dp_x(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInternalState) -> MicroArchAction {
todo!()
Expand Down

0 comments on commit 3bd1d98

Please sign in to comment.