From c40a565a9764164c2368cca83f200a12c6fdeda1 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?kleines=20Filmr=C3=B6llchen?= <filmroellchen@serenityos.org>
Date: Sun, 8 Sep 2024 15:02:04 +0200
Subject: [PATCH] sapemu: Actually check final CPU state

Some test regressions (and a small nop fix), 72/256
---
 sapemu/src/smp/ops.rs |  3 ++-
 sapemu/src/test.rs    | 22 ++++++++++++++++++++--
 2 files changed, 22 insertions(+), 3 deletions(-)

diff --git a/sapemu/src/smp/ops.rs b/sapemu/src/smp/ops.rs
index 57b5656..12b9074 100644
--- a/sapemu/src/smp/ops.rs
+++ b/sapemu/src/smp/ops.rs
@@ -369,7 +369,8 @@ fn nop(cpu: &mut Smp, memory: &mut Memory, cycle: usize, state: InstructionInter
 	debug_instruction!("nop", cycle, cpu);
 
 	match cycle {
-		0 => MicroArchAction::Next,
+		0 => MicroArchAction::Continue(state),
+		1 => MicroArchAction::Next,
 		_ => unreachable!(),
 	}
 }
diff --git a/sapemu/src/test.rs b/sapemu/src/test.rs
index 7f46b09..be88d95 100644
--- a/sapemu/src/test.rs
+++ b/sapemu/src/test.rs
@@ -14,6 +14,7 @@
 
 #![allow(unused)]
 
+use bitflags::Flags;
 use log::info;
 use rstest::rstest;
 use serde::Deserialize;
@@ -63,6 +64,17 @@ impl From<&ProcessorState> for Smp {
 	}
 }
 
+impl PartialEq<Smp> for ProcessorState {
+	fn eq(&self, other: &Smp) -> bool {
+		self.pc == other.pc
+			&& self.a == other.a
+			&& self.x == other.x
+			&& self.y == other.y
+			&& self.sp == other.sp
+			&& self.psw == other.psw.bits()
+	}
+}
+
 #[derive(Deserialize, Debug, Clone)]
 #[repr(transparent)]
 struct RamState(Vec<MemoryCellState>);
@@ -241,11 +253,17 @@ fn single_instruction(
 				memory.copy_mapped_registers_from_smp(&smp);
 				assert!(
 					test.final_state.ram == memory,
-					"result mismatch at test {}: {}",
+					"memory mismatch at test {}: {}",
 					test.name,
 					test.final_state.ram.mismatch_info(&memory)
 				);
-				// TODO: check CPU state.
+				assert!(
+					test.final_state == smp,
+					"cpu mismatch at test {}:\nexpected {:?}\ngot {:?}",
+					test.name,
+					test.final_state,
+					smp,
+				);
 			}
 		},
 		Err(why) => {