fix ESP32C3 gpio interrupt and add initial support to saradc

lcgamboa · Dec 17, 2023 · 321de74 · 321de74
1 parent 1eef4ad
commit 321de74
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Showing 4 changed files with 44 additions and 5 deletions.
diff --git a/hw/gpio/esp32c3_gpio.c b/hw/gpio/esp32c3_gpio.c
@@ -42,7 +42,7 @@ static uint64_t esp32c3_gpio_read(void *opaque, hwaddr addr, unsigned int size)
             r = s->gpio_status;
             break;
         case 0x5C: //GPIO_PCPU_INT_REG
-            r = s->gpio_pcpu_int;
+            r = s->gpio_acpu_int; //using ESP32 GPIO support
             break;
         default:
             break;

diff --git a/hw/misc/esp32c3_saradc.c b/hw/misc/esp32c3_saradc.c
@@ -15,6 +15,12 @@
 
 #define DEBUG 0
 
+unsigned short ADC_values[31]={31,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,
+                               24,25,26,27,28,29,30};
+
+static int channel1=0;
+static int channel2=0;
+
 static uint64_t esp32c3_saradc_read(void *opaque, hwaddr addr, unsigned int size)
 {   
     Esp32c3SarAdcState *s = ESP32C3_SARADC(opaque);
@@ -26,6 +32,12 @@ static uint64_t esp32c3_saradc_read(void *opaque, hwaddr addr, unsigned int size
             r=FIELD_DP32(r, APB_SARADC_INT_RAW_REG, APB_SARADC_ADC1_DONE_INT_RAW, 1);
             r=FIELD_DP32(r, APB_SARADC_INT_RAW_REG, APB_SARADC_ADC2_DONE_INT_RAW, 1);
             break;
+        case A_APB_SARADC_1_DATA_STATUS_REG:   
+            r= ADC_values[channel1];
+            break; 
+        case A_APB_SARADC_2_DATA_STATUS_REG:   
+            r= ADC_values[channel2];
+            break;     
     }
 
     if(DEBUG) printf("esp32_saradc_read  0x%04lx= 0x%08x\n",(unsigned long) addr,r);
@@ -40,6 +52,19 @@ static void esp32c3_saradc_write(void *opaque, hwaddr addr,
 
     if(DEBUG) printf("esp32_saradc_write 0x%04lx= 0x%08lx\n",(unsigned long) addr, (unsigned long) value);
 
+        switch(addr) {
+        case A_APB_SARADC_ONETIME_SAMPLE_REG:   
+            if(FIELD_EX32(value, APB_SARADC_ONETIME_SAMPLE_REG, APB_SARADC1_ONETIME_SAMPLE))
+            {
+                channel1=FIELD_EX32(value, APB_SARADC_ONETIME_SAMPLE_REG, APB_SARADC_ONETIME_CHANNEL);
+            } 
+            if(FIELD_EX32(value, APB_SARADC_ONETIME_SAMPLE_REG, APB_SARADC2_ONETIME_SAMPLE))
+            {
+                channel2=FIELD_EX32(value, APB_SARADC_ONETIME_SAMPLE_REG, APB_SARADC_ONETIME_CHANNEL);
+            } 
+            break; 
+    }
+
     s->mem[addr/4]=value;
 }
 

diff --git a/hw/riscv/esp32c3_picsimlab.c b/hw/riscv/esp32c3_picsimlab.c
@@ -280,11 +280,11 @@ void qemu_picsimlab_set_pin(int pin,int value)
    //qemu_mutex_unlock_iothread ();
 }
 
-//extern unsigned short ADC_values[31];
+extern unsigned short ADC_values[31];
 
 void qemu_picsimlab_set_apin(int chn,int value)
 {
-   //ADC_values[chn] = value;
+   ADC_values[chn] = value;
 }
 
 int qemu_picsimlab_flash_dump( int64_t offset, void *buf, int bytes)
@@ -708,6 +708,8 @@ static void esp32c3_machine_init(MachineState *machine)
         sysbus_realize(SYS_BUS_DEVICE(&ms->gpio), &error_fatal);
         MemoryRegion *mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&ms->gpio), 0);
         memory_region_add_subregion_overlap(sys_mem, DR_REG_GPIO_BASE, mr, 0);
+        sysbus_connect_irq(SYS_BUS_DEVICE(&ms->gpio), 0,
+                           qdev_get_gpio_in(intmatrix_dev, ETS_GPIO_INTR_SOURCE));
     }
 
     /* (Extmem) Cache realization */

diff --git a/include/hw/misc/esp32c3_saradc.h b/include/hw/misc/esp32c3_saradc.h
@@ -15,6 +15,18 @@ typedef struct Esp32c3SarAdcState {
 } Esp32c3SarAdcState;
 
 REG32(APB_SARADC_INT_RAW_REG , 0x044);
-  FIELD(APB_SARADC_INT_RAW_REG, APB_SARADC_ADC1_DONE_INT_RAW, 31, 1)
-  FIELD(APB_SARADC_INT_RAW_REG, APB_SARADC_ADC2_DONE_INT_RAW, 30, 1)
+  FIELD(APB_SARADC_INT_RAW_REG, APB_SARADC_ADC1_DONE_INT_RAW, 31, 1);
+  FIELD(APB_SARADC_INT_RAW_REG, APB_SARADC_ADC2_DONE_INT_RAW, 30, 1);
 
+REG32(APB_SARADC_ONETIME_SAMPLE_REG, 0x20); 
+  FIELD(APB_SARADC_ONETIME_SAMPLE_REG, APB_SARADC1_ONETIME_SAMPLE, 31, 1);
+  FIELD(APB_SARADC_ONETIME_SAMPLE_REG, APB_SARADC2_ONETIME_SAMPLE, 30, 1);
+  FIELD(APB_SARADC_ONETIME_SAMPLE_REG, APB_SARADC_ONETIME_START, 29, 1);
+  FIELD(APB_SARADC_ONETIME_SAMPLE_REG, APB_SARADC_ONETIME_CHANNEL,25,4);  
+  FIELD(APB_SARADC_ONETIME_SAMPLE_REG,APB_SARADC_ONETIME_ATTEN, 23, 2);
+
+REG32(APB_SARADC_1_DATA_STATUS_REG, 0x2C);
+  FIELD(APB_SARADC_1_DATA_STATUS_REG, APB_SARADC_ADC1_DATA,0, 17);
+
+REG32(APB_SARADC_2_DATA_STATUS_REG, 0x3C);
+  FIELD(APB_SARADC_2_DATA_STATUS_REG, APB_SARADC_ADC2_DATA,0, 17);