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gba_memory.c
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gba_memory.c
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/* gameplaySP
*
* Copyright (C) 2006 Exophase <exophase@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "common.h"
#include "streams/file_stream.h"
/* Sound */
#define gbc_sound_tone_control_low(channel, regn) \
{ \
render_gbc_sound(); \
u32 initial_volume = (value >> 12) & 0x0F; \
u32 envelope_ticks = ((value >> 8) & 0x07) * 4; \
gbc_sound_channel[channel].length_ticks = 64 - (value & 0x3F); \
gbc_sound_channel[channel].sample_table_idx = ((value >> 6) & 0x03); \
gbc_sound_channel[channel].envelope_direction = (value >> 11) & 0x01; \
gbc_sound_channel[channel].envelope_initial_volume = initial_volume; \
gbc_sound_channel[channel].envelope_volume = initial_volume; \
gbc_sound_channel[channel].envelope_initial_ticks = envelope_ticks; \
gbc_sound_channel[channel].envelope_ticks = envelope_ticks; \
gbc_sound_channel[channel].envelope_status = (envelope_ticks != 0); \
gbc_sound_channel[channel].envelope_volume = initial_volume; \
write_ioreg(regn, value); \
} \
#define gbc_sound_tone_control_high(channel, regn) \
{ \
render_gbc_sound(); \
u32 rate = value & 0x7FF; \
gbc_sound_channel[channel].rate = rate; \
gbc_sound_channel[channel].frequency_step = \
float_to_fp16_16(((131072.0 / (2048 - rate)) * 8.0) / sound_frequency); \
gbc_sound_channel[channel].length_status = (value >> 14) & 0x01; \
if(value & 0x8000) \
{ \
gbc_sound_channel[channel].active_flag = 1; \
gbc_sound_channel[channel].sample_index -= float_to_fp16_16(1.0 / 12.0); \
gbc_sound_channel[channel].envelope_ticks = \
gbc_sound_channel[channel].envelope_initial_ticks; \
gbc_sound_channel[channel].envelope_volume = \
gbc_sound_channel[channel].envelope_initial_volume; \
} \
\
write_ioreg(regn, value & 0x47FF); \
} \
#define gbc_sound_tone_control_sweep() \
{ \
render_gbc_sound(); \
value &= 0x007F; \
u32 sweep_ticks = ((value >> 4) & 0x07) * 2; \
gbc_sound_channel[0].sweep_shift = value & 0x07; \
gbc_sound_channel[0].sweep_direction = (value >> 3) & 0x01; \
gbc_sound_channel[0].sweep_status = (value != 8); \
gbc_sound_channel[0].sweep_ticks = sweep_ticks; \
gbc_sound_channel[0].sweep_initial_ticks = sweep_ticks; \
write_ioreg(REG_SOUND1CNT_L, value); \
} \
#define gbc_sound_wave_control() \
{ \
render_gbc_sound(); \
gbc_sound_channel[2].wave_type = (value >> 5) & 0x01; \
gbc_sound_channel[2].wave_bank = (value >> 6) & 0x01; \
gbc_sound_channel[2].master_enable = 0; \
if(value & 0x80) \
gbc_sound_channel[2].master_enable = 1; \
\
write_ioreg(REG_SOUND3CNT_L, value & 0x00E0); \
} \
static const u32 gbc_sound_wave_volume[4] = { 0, 16384, 8192, 4096 };
#define gbc_sound_tone_control_low_wave() \
{ \
render_gbc_sound(); \
gbc_sound_channel[2].length_ticks = 256 - (value & 0xFF); \
if((value >> 15) & 0x01) \
gbc_sound_channel[2].wave_volume = 12288; \
else \
gbc_sound_channel[2].wave_volume = \
gbc_sound_wave_volume[(value >> 13) & 0x03]; \
write_ioreg(REG_SOUND3CNT_H, value); \
} \
#define gbc_sound_tone_control_high_wave() \
{ \
render_gbc_sound(); \
u32 rate = value & 0x7FF; \
gbc_sound_channel[2].rate = rate; \
gbc_sound_channel[2].frequency_step = \
float_to_fp16_16((2097152.0 / (2048 - rate)) / sound_frequency); \
gbc_sound_channel[2].length_status = (value >> 14) & 0x01; \
if(value & 0x8000) \
{ \
gbc_sound_channel[2].sample_index = 0; \
gbc_sound_channel[2].active_flag = 1; \
} \
write_ioreg(REG_SOUND3CNT_X, value); \
} \
#define gbc_sound_noise_control() \
{ \
u32 dividing_ratio = value & 0x07; \
u32 frequency_shift = (value >> 4) & 0x0F; \
render_gbc_sound(); \
if(dividing_ratio == 0) \
{ \
gbc_sound_channel[3].frequency_step = \
float_to_fp16_16(1048576.0 / (1 << (frequency_shift + 1)) / \
sound_frequency); \
} \
else \
{ \
gbc_sound_channel[3].frequency_step = \
float_to_fp16_16(524288.0 / (dividing_ratio * \
(1 << (frequency_shift + 1))) / sound_frequency); \
} \
gbc_sound_channel[3].noise_type = (value >> 3) & 0x01; \
gbc_sound_channel[3].length_status = (value >> 14) & 0x01; \
if(value & 0x8000) \
{ \
gbc_sound_channel[3].sample_index = 0; \
gbc_sound_channel[3].active_flag = 1; \
gbc_sound_channel[3].envelope_ticks = \
gbc_sound_channel[3].envelope_initial_ticks; \
gbc_sound_channel[3].envelope_volume = \
gbc_sound_channel[3].envelope_initial_volume; \
} \
write_ioreg(REG_SOUND4CNT_H, value & 0x40FF); \
} \
static void gbc_trigger_sound(u32 value)
{
u32 channel;
render_gbc_sound();
/* Trigger all 4 GBC sound channels */
for (channel = 0; channel < 4; channel++)
{
gbc_sound_master_volume_right = value & 0x07;
gbc_sound_master_volume_left = (value >> 4) & 0x07;
gbc_sound_channel[channel].status =
(((value >> (channel + 8)) & 0x1) | ((value >> (channel + 11)) & 0x3));
}
write_ioreg(REG_SOUNDCNT_L, value & 0xFF77);
}
#define trigger_sound() \
{ \
render_gbc_sound(); \
timer[0].direct_sound_channels = \
((((value >> 10) & 0x01) == 0) | ((((value >> 14) & 0x01) == 0) << 1)); \
timer[1].direct_sound_channels = \
((((value >> 10) & 0x01) == 1) | ((((value >> 14) & 0x01) == 1) << 1)); \
direct_sound_channel[0].volume_halve = ((~(value >> 2)) & 0x01); \
direct_sound_channel[0].status = ((value >> 8) & 0x03); \
direct_sound_channel[1].volume_halve = ((~(value >> 3)) & 0x01); \
direct_sound_channel[1].status = ((value >> 12) & 0x03); \
gbc_sound_master_volume = value & 0x03; \
\
if((value >> 11) & 0x01) \
sound_reset_fifo(0); \
if((value >> 15) & 0x01) \
sound_reset_fifo(1); \
write_ioreg(REG_SOUNDCNT_H, value & 0x770F); \
} \
static void sound_control_x(u32 value)
{
render_gbc_sound();
if (value & 0x80)
{
if (sound_on != 1)
sound_on = 1;
}
else
{
u32 i;
for (i = 0; i < 4; i++)
gbc_sound_channel[i].active_flag = 0;
sound_on = 0;
}
value = (value & 0xFFF0) | (read_ioreg(REG_SOUNDCNT_X) & 0x000F);
write_ioreg(REG_SOUNDCNT_X, value);
}
#define sound_update_frequency_step(timer_number) \
timer[timer_number].frequency_step = \
float_to_fp8_24((GBC_BASE_RATE / sound_frequency) / (timer_reload)) \
/* Main */
extern timer_type timer[4];
static const u32 prescale_table[] = { 0, 6, 8, 10 };
#define count_timer(timer_number) \
timer[timer_number].reload = 0x10000 - value; \
if(timer_number < 2) \
{ \
u32 timer_reload = \
timer[timer_number].reload << timer[timer_number].prescale; \
sound_update_frequency_step(timer_number); \
} \
#define adjust_sound_buffer(timer_number, channel) \
if(timer[timer_number].direct_sound_channels & (0x01 << channel)) \
{ \
direct_sound_channel[channel].buffer_index = \
(gbc_sound_buffer_index + buffer_adjust) % BUFFER_SIZE; \
} \
static void trigger_timer(u32 timer_number, u32 value)
{
if (value & 0x80)
{
if(timer[timer_number].status == TIMER_INACTIVE)
{
u32 prescale = prescale_table[value & 0x03];
u32 timer_reload = timer[timer_number].reload;
if((value >> 2) & 0x01)
timer[timer_number].status = TIMER_CASCADE;
else
timer[timer_number].status = TIMER_PRESCALE;
timer[timer_number].prescale = prescale;
timer[timer_number].irq = ((value >> 6) & 0x1);
write_ioreg(REG_TMXD(timer_number), (u32)(-timer_reload));
timer_reload <<= prescale;
timer[timer_number].count = timer_reload;
if(timer_reload < execute_cycles)
execute_cycles = timer_reload;
if(timer_number < 2)
{
u32 buffer_adjust =
(u32)(((float)(cpu_ticks - gbc_sound_last_cpu_ticks) *
sound_frequency) / GBC_BASE_RATE) * 2;
sound_update_frequency_step(timer_number);
adjust_sound_buffer(timer_number, 0);
adjust_sound_buffer(timer_number, 1);
}
}
}
else
{
if(timer[timer_number].status != TIMER_INACTIVE)
{
timer[timer_number].status = TIMER_INACTIVE;
}
}
write_ioreg(REG_TMXCNT(timer_number), value);
}
/* Memory timings */
const u8 ws012_nonseq[] = {4, 3, 2, 8};
const u8 ws0_seq[] = {2, 1};
const u8 ws1_seq[] = {4, 1};
const u8 ws2_seq[] = {8, 1};
/* Divided by region and bus width (16/32) */
u8 ws_cyc_seq[16][2] =
{
{ 1, 1 }, // BIOS
{ 1, 1 }, // Invalid
{ 3, 6 }, // EWRAM (default settings)
{ 1, 1 }, // IWRAM
{ 1, 1 }, // IO Registers
{ 1, 2 }, // Palette RAM
{ 1, 2 }, // VRAM
{ 1, 2 }, // OAM
{ 0, 0 }, // Gamepak (wait 0)
{ 0, 0 }, // Gamepak (wait 0)
{ 0, 0 }, // Gamepak (wait 1)
{ 0, 0 }, // Gamepak (wait 1)
{ 0, 0 }, // Gamepak (wait 2)
{ 0, 0 }, // Gamepak (wait 2)
{ 1, 1 }, // Invalid
{ 1, 1 }, // Invalid
};
u8 ws_cyc_nseq[16][2] =
{
{ 1, 1 }, // BIOS
{ 1, 1 }, // Invalid
{ 3, 6 }, // EWRAM (default settings)
{ 1, 1 }, // IWRAM
{ 1, 1 }, // IO Registers
{ 1, 2 }, // Palette RAM
{ 1, 2 }, // VRAM
{ 1, 2 }, // OAM
{ 0, 0 }, // Gamepak (wait 0)
{ 0, 0 }, // Gamepak (wait 0)
{ 0, 0 }, // Gamepak (wait 1)
{ 0, 0 }, // Gamepak (wait 1)
{ 0, 0 }, // Gamepak (wait 2)
{ 0, 0 }, // Gamepak (wait 2)
{ 1, 1 }, // Invalid
{ 1, 1 }, // Invalid
};
const u32 def_seq_cycles[16][2] =
{
{ 1, 1 }, // BIOS
{ 1, 1 }, // Invalid
{ 3, 6 }, // EWRAM (default settings)
{ 1, 1 }, // IWRAM
{ 1, 1 }, // IO Registers
{ 1, 2 }, // Palette RAM
{ 1, 2 }, // VRAM
{ 1, 2 }, // OAM
{ 3, 6 }, // Gamepak (wait 0)
{ 3, 6 }, // Gamepak (wait 0)
{ 5, 9 }, // Gamepak (wait 1)
{ 5, 9 }, // Gamepak (wait 1)
{ 9, 17 }, // Gamepak (wait 2)
{ 9, 17 }, // Gamepak (wait 2)
};
u8 bios_rom[1024 * 16];
// Up to 128kb, store SRAM, flash ROM, or EEPROM here.
u8 gamepak_backup[1024 * 128];
u32 dma_bus_val;
dma_transfer_type dma[4];
// ROM memory is allocated in blocks of 1MB to better map the native block
// mapping system. We will try to allocate 32 of them to allow loading
// ROMs up to 32MB, but we might fail on memory constrained systems.
u8 *gamepak_buffers[32]; /* Pointers to malloc'ed blocks */
u32 gamepak_buffer_count; /* Value between 1 and 32 */
u32 gamepak_size; /* Size of the ROM in bytes */
// We allocate in 1MB chunks.
const unsigned gamepak_buffer_blocksize = 1024*1024;
// LRU queue with the loaded blocks and what they map to
struct {
u16 next_lru; /* Index in the struct to the next LRU entry */
s16 phy_rom; /* ROM page number (-1 means not mapped) */
} gamepak_blk_queue[1024];
u16 gamepak_lru_head;
u16 gamepak_lru_tail;
// Stick page bit: prevents page eviction for a frame. This is used to prevent
// unmapping code pages while being used (ie. in the interpreter).
u32 gamepak_sticky_bit[1024/32];
#define gamepak_sb_test(idx) \
(gamepak_sticky_bit[((unsigned)(idx)) >> 5] & (1 << (((unsigned)(idx)) & 31)))
// This is global so that it can be kept open for large ROMs to swap
// pages from, so there's no slowdown with opening and closing the file
// a lot.
RFILE *gamepak_file_large = NULL;
// Writes to these respective locations should trigger an update
// so the related subsystem may react to it.
// If the GBC audio waveform is modified:
u32 gbc_sound_wave_update = 0;
u32 backup_type = BACKUP_UNKN;
u32 backup_type_reset = BACKUP_UNKN;
u32 flash_mode = FLASH_BASE_MODE;
u32 flash_command_position = 0;
u32 flash_bank_num; // 0 or 1
u32 flash_bank_cnt;
u32 flash_device_id = FLASH_DEVICE_MACRONIX_64KB;
void reload_timing_info()
{
int i;
uint16_t waitcnt = read_ioreg(REG_WAITCNT);
/* Sequential 16 and 32 bit accesses to ROM */
ws_cyc_seq[0x8][0] = ws_cyc_seq[0x9][0] = 1 + ws0_seq[(waitcnt >> 4) & 1];
ws_cyc_seq[0xA][0] = ws_cyc_seq[0xB][0] = 1 + ws1_seq[(waitcnt >> 7) & 1];
ws_cyc_seq[0xC][0] = ws_cyc_seq[0xD][0] = 1 + ws2_seq[(waitcnt >> 10) & 1];
for (i = 0x8; i <= 0xD; i++)
{
/* 32 bit accesses just cost double due to 16 bit bus */
ws_cyc_seq[i][1] = ws_cyc_seq[i][0] * 2;
}
/* Sequential 16 and 32 bit accesses to ROM */
ws_cyc_nseq[0x8][0] = ws_cyc_nseq[0x9][0] = 1 + ws012_nonseq[(waitcnt >> 2) & 3];
ws_cyc_nseq[0xA][0] = ws_cyc_nseq[0xB][0] = 1 + ws012_nonseq[(waitcnt >> 5) & 3];
ws_cyc_nseq[0xC][0] = ws_cyc_nseq[0xD][0] = 1 + ws012_nonseq[(waitcnt >> 8) & 3];
for (i = 0x8; i <= 0xD; i++)
{
/* 32 bit accesses are a non-seq (16) + seq access (16) */
ws_cyc_nseq[i][1] = 1 + ws_cyc_nseq[i][0] + ws_cyc_seq[i][0];
}
}
u8 read_backup(u32 address)
{
u8 value = 0;
if(backup_type == BACKUP_EEPROM)
return 0xff;
if(backup_type == BACKUP_UNKN)
backup_type = BACKUP_SRAM;
if(backup_type == BACKUP_SRAM)
value = gamepak_backup[address];
else if(flash_mode == FLASH_ID_MODE)
{
if (flash_bank_cnt == FLASH_SIZE_128KB)
{
/* ID manufacturer type */
if(address == 0x0000)
value = FLASH_MANUFACTURER_MACRONIX;
/* ID device type */
else if(address == 0x0001)
value = FLASH_DEVICE_MACRONIX_128KB;
}
else
{
/* ID manufacturer type */
if(address == 0x0000)
value = FLASH_MANUFACTURER_PANASONIC;
/* ID device type */
else if(address == 0x0001)
value = FLASH_DEVICE_PANASONIC_64KB;
}
}
else
{
u32 fulladdr = address + 64*1024*flash_bank_num;
value = gamepak_backup[fulladdr];
}
return value;
}
#define read_backup8() \
value = read_backup(address & 0xFFFF); \
#define read_backup16() \
value = read_backup(address & 0xFFFF); \
value = value | (value << 8);
#define read_backup32() \
value = read_backup(address & 0xFFFF); \
value = value | (value << 8); \
value = value | (value << 16);
#define write_eeprom8(addr, value)
#define write_eeprom16(addr, value) \
write_eeprom(addr, value)
#define write_eeprom32(addr, value)
// EEPROM is 512 bytes by default; it is autodetecte as 8KB if
// 14bit address DMAs are made (this is done in the DMA handler).
u32 eeprom_size = EEPROM_512_BYTE;
u32 eeprom_mode = EEPROM_BASE_MODE;
u32 eeprom_address = 0;
u32 eeprom_counter = 0;
void function_cc write_eeprom(u32 unused_address, u32 value)
{
switch(eeprom_mode)
{
case EEPROM_BASE_MODE:
backup_type = BACKUP_EEPROM;
eeprom_address |= (value & 0x01) << (1 - eeprom_counter);
if(++eeprom_counter == 2)
{
switch(eeprom_address & 0x03)
{
case 0x02:
eeprom_mode = EEPROM_WRITE_ADDRESS_MODE;
break;
case 0x03:
eeprom_mode = EEPROM_ADDRESS_MODE;
break;
}
eeprom_counter = 0;
eeprom_address = 0;
}
break;
case EEPROM_ADDRESS_MODE:
case EEPROM_WRITE_ADDRESS_MODE:
eeprom_address |= (value & 0x01) << (15 - (eeprom_counter % 16));
if(++eeprom_counter == (eeprom_size == EEPROM_512_BYTE ? 6 : 14))
{
eeprom_counter = 0;
if (eeprom_size == EEPROM_512_BYTE)
eeprom_address >>= 10; // Addr is just 6 bits (drop 10LSB)
else
eeprom_address >>= 2; // Addr is 14 bits (drop 2LSB)
eeprom_address <<= 3; // EEPROM accessed in blocks of 8 bytes
if(eeprom_mode == EEPROM_ADDRESS_MODE)
eeprom_mode = EEPROM_ADDRESS_FOOTER_MODE;
else
{
eeprom_mode = EEPROM_WRITE_MODE;
memset(gamepak_backup + eeprom_address, 0, 8);
}
}
break;
case EEPROM_WRITE_MODE:
gamepak_backup[eeprom_address + (eeprom_counter / 8)] |=
(value & 0x01) << (7 - (eeprom_counter % 8));
eeprom_counter++;
if(eeprom_counter == 64)
{
eeprom_counter = 0;
eeprom_mode = EEPROM_WRITE_FOOTER_MODE;
}
break;
case EEPROM_ADDRESS_FOOTER_MODE:
case EEPROM_WRITE_FOOTER_MODE:
eeprom_counter = 0;
if(eeprom_mode == EEPROM_ADDRESS_FOOTER_MODE)
eeprom_mode = EEPROM_READ_HEADER_MODE;
else
eeprom_mode = EEPROM_BASE_MODE;
break;
default:
break;
}
}
#define read_memory_gamepak(type) \
u32 gamepak_index = address >> 15; \
u8 *map = memory_map_read[gamepak_index]; \
\
if(!map) \
map = load_gamepak_page(gamepak_index & 0x3FF); \
\
value = readaddress##type(map, address & 0x7FFF) \
#define unmapped_rom_read8(addr) \
(((addr) >> 1) >> (((addr) & 1) * 8)) & 0xFF
#define unmapped_rom_read16(addr) \
((addr) >> 1) & 0xFFFF
#define unmapped_rom_read32(addr) \
((((addr) & ~3) >> 1) & 0xFFFF) | (((((addr) & ~3) + 2) >> 1) << 16)
#define read_open8() \
if(!(reg[REG_CPSR] & 0x20)) \
value = read_memory8(reg[REG_PC] + 8 + (address & 0x03)); \
else \
value = read_memory8(reg[REG_PC] + 4 + (address & 0x01)) \
#define read_open16() \
if(!(reg[REG_CPSR] & 0x20)) \
value = read_memory16(reg[REG_PC] + 8 + (address & 0x02)); \
else \
value = read_memory16(reg[REG_PC] + 4) \
#define read_open32() \
if(!(reg[REG_CPSR] & 0x20)) \
value = read_memory32(reg[REG_PC] + 8); \
else \
{ \
u32 current_instruction = read_memory16(reg[REG_PC] + 4); \
value = current_instruction | (current_instruction << 16); \
} \
u32 function_cc read_eeprom(void)
{
u32 value;
switch(eeprom_mode)
{
case EEPROM_BASE_MODE:
value = 1;
break;
case EEPROM_READ_MODE:
value = (gamepak_backup[eeprom_address + (eeprom_counter / 8)] >>
(7 - (eeprom_counter % 8))) & 0x01;
eeprom_counter++;
if(eeprom_counter == 64)
{
eeprom_counter = 0;
eeprom_mode = EEPROM_BASE_MODE;
}
break;
case EEPROM_READ_HEADER_MODE:
value = 0;
eeprom_counter++;
if(eeprom_counter == 4)
{
eeprom_mode = EEPROM_READ_MODE;
eeprom_counter = 0;
}
break;
default:
value = 0;
break;
}
return value;
}
#define read_memory(type) \
switch(address >> 24) \
{ \
case 0x00: \
/* BIOS */ \
if (address < 0x4000) { \
if(reg[REG_PC] >= 0x4000) \
value = (u##type)(reg[REG_BUS_VALUE] >> ((address & 0x03) << 3)); \
else \
value = readaddress##type(bios_rom, address & 0x3FFF); \
} else { \
read_open##type(); \
} \
break; \
\
case 0x02: \
/* external work RAM */ \
value = readaddress##type(ewram, (address & 0x3FFFF)); \
break; \
\
case 0x03: \
/* internal work RAM */ \
value = readaddress##type(iwram, (address & 0x7FFF) + 0x8000); \
break; \
\
case 0x04: \
/* I/O registers */ \
value = readaddress##type(io_registers, address & 0x3FF); \
break; \
\
case 0x05: \
/* palette RAM */ \
value = readaddress##type(palette_ram, address & 0x3FF); \
break; \
\
case 0x06: \
/* VRAM */ \
address &= 0x1FFFF; \
if(address >= 0x18000) \
address -= 0x8000; \
\
value = readaddress##type(vram, address); \
break; \
\
case 0x07: \
/* OAM RAM */ \
value = readaddress##type(oam_ram, address & 0x3FF); \
break; \
\
case 0x0D: \
if (backup_type == BACKUP_EEPROM) { \
value = read_eeprom(); \
break; \
} \
/* fallthrough */ \
case 0x08: \
case 0x09: \
case 0x0A: \
case 0x0B: \
case 0x0C: \
/* gamepak ROM */ \
if((address & 0x1FFFFFF) >= gamepak_size) \
value = unmapped_rom_read##type(address); \
else \
{ \
read_memory_gamepak(type); \
} \
break; \
\
case 0x0E: \
case 0x0F: \
read_backup##type(); \
break; \
\
default: \
read_open##type(); \
break; \
} \
static cpu_alert_type trigger_dma(u32 dma_number, u32 value)
{
if(value & 0x8000)
{
if(dma[dma_number].start_type == DMA_INACTIVE)
{
u32 start_type = ((value >> 12) & 0x03);
u32 src_address = 0xFFFFFFF & (read_dmareg(REG_DMA0SAD, dma_number) |
(read_dmareg(REG_DMA0SAD + 1, dma_number) << 16));
u32 dst_address = 0xFFFFFFF & (read_dmareg(REG_DMA0DAD, dma_number) |
(read_dmareg(REG_DMA0DAD + 1, dma_number) << 16));
dma[dma_number].source_address = src_address;
dma[dma_number].dest_address = dst_address;
dma[dma_number].source_direction = ((value >> 7) & 3);
dma[dma_number].repeat_type = ((value >> 9) & 0x01);
dma[dma_number].start_type = start_type;
dma[dma_number].irq = ((value >> 14) & 0x1);
/* If it is sound FIFO DMA make sure the settings are a certain way */
if((dma_number >= 1) && (dma_number <= 2) &&
(start_type == DMA_START_SPECIAL))
{
dma[dma_number].length_type = DMA_32BIT;
dma[dma_number].length = 4;
dma[dma_number].dest_direction = DMA_FIXED;
if(dst_address == 0x40000A4)
dma[dma_number].direct_sound_channel = DMA_DIRECT_SOUND_B;
else
dma[dma_number].direct_sound_channel = DMA_DIRECT_SOUND_A;
}
else
{
u32 length = read_dmareg(REG_DMA0CNT_L, dma_number);
if((dma_number == 3) && ((dst_address >> 24) == 0x0D) &&
((length & 0x1F) == 17))
eeprom_size = EEPROM_8_KBYTE;
if(dma_number < 3)
length &= 0x3FFF;
if(length == 0)
{
if(dma_number == 3)
length = 0x10000;
else
length = 0x04000;
}
dma[dma_number].length = length;
dma[dma_number].length_type = ((value >> 10) & 0x01);
dma[dma_number].dest_direction = ((value >> 5) & 3);
}
write_dmareg(REG_DMA0CNT_H, dma_number, value);
if(start_type == DMA_START_IMMEDIATELY) {
// Excutes the DMA now! Copies the data and returns side effects.
int dma_cycles = 0;
cpu_alert_type ret = dma_transfer(dma_number, &dma_cycles);
if (!dma_cycles)
return ret;
// Sleep CPU for N cycles and return HALT as side effect (so it does).
reg[CPU_HALT_STATE] = CPU_DMA;
reg[REG_SLEEP_CYCLES] = 0x80000000 | (u32)dma_cycles;
return CPU_ALERT_HALT | ret;
}
}
}
else
{
dma[dma_number].start_type = DMA_INACTIVE;
dma[dma_number].direct_sound_channel = DMA_NO_DIRECT_SOUND;
write_dmareg(REG_DMA0CNT_H, dma_number, value);
}
return CPU_ALERT_NONE;
}
static inline s32 signext28(u32 value)
{
s32 ret = (s32)(value << 4);
return ret >> 4;
}
cpu_alert_type function_cc write_io_register16(u32 address, u32 value)
{
uint16_t ioreg = (address & 0x3FE) >> 1;
value &= 0xffff;
switch(ioreg)
{
case REG_DISPCNT:
// Changing the lowest 3 bits might require object re-sorting
reg[OAM_UPDATED] |= ((value & 0x07) != (read_ioreg(REG_DISPCNT) & 0x07));
write_ioreg(REG_DISPCNT, value);
break;
// DISPSTAT has 3 read only bits, controlled by the LCD controller
case REG_DISPSTAT:
write_ioreg(REG_DISPSTAT, (read_ioreg(REG_DISPSTAT) & 0x07) | (value & ~0x07));
break;
// BG2 reference X
case REG_BG2X_L:
case REG_BG2X_H:
write_ioreg(ioreg, value);
affine_reference_x[0] = signext28(read_ioreg32(REG_BG2X_L));
break;
// BG2 reference Y
case REG_BG2Y_L:
case REG_BG2Y_H:
write_ioreg(ioreg, value);
affine_reference_y[0] = signext28(read_ioreg32(REG_BG2Y_L));
break;
// BG3 reference X
case REG_BG3X_L:
case REG_BG3X_H:
write_ioreg(ioreg, value);
affine_reference_x[1] = signext28(read_ioreg32(REG_BG3X_L));
break;
// BG3 reference Y
case REG_BG3Y_L:
case REG_BG3Y_H:
write_ioreg(ioreg, value);
affine_reference_y[1] = signext28(read_ioreg32(REG_BG3Y_L));
break;
// Sound 1 registers
case REG_SOUND1CNT_L: // control sweep
gbc_sound_tone_control_sweep();
break;
case REG_SOUND1CNT_H: // control duty/length/envelope
gbc_sound_tone_control_low(0, REG_SOUND1CNT_H);
break;
case REG_SOUND1CNT_X: // control frequency
gbc_sound_tone_control_high(0, REG_SOUND1CNT_X);
break;
// Sound 2 registers
case REG_SOUND2CNT_L: // control duty/length/envelope
gbc_sound_tone_control_low(1, REG_SOUND2CNT_L);
break;
case REG_SOUND2CNT_H: // control frequency
gbc_sound_tone_control_high(1, REG_SOUND2CNT_H);
break;
// Sound 3 registers
case REG_SOUND3CNT_L: // control wave
gbc_sound_wave_control();
break;
case REG_SOUND3CNT_H: // control length/volume
gbc_sound_tone_control_low_wave();
break;
case REG_SOUND3CNT_X: // control frequency
gbc_sound_tone_control_high_wave();
break;
// Sound 4 registers
case REG_SOUND4CNT_L: // length/envelope
gbc_sound_tone_control_low(3, REG_SOUND4CNT_L);
break;
case REG_SOUND4CNT_H: // control frequency
gbc_sound_noise_control();
break;
// Sound control registers
case REG_SOUNDCNT_L:
gbc_trigger_sound(value);
break;
case REG_SOUNDCNT_H:
trigger_sound();
break;
case REG_SOUNDCNT_X:
sound_control_x(value);
break;
// Sound wave RAM, flag wave table update
case REG_SOUNDWAVE_0 ... REG_SOUNDWAVE_7:
render_gbc_sound();
gbc_sound_wave_update = 1;
write_ioreg(ioreg, value);
break;
// DMA control register: can cause an IRQ
case REG_DMA0CNT_H: return trigger_dma(0, value);
case REG_DMA1CNT_H: return trigger_dma(1, value);
case REG_DMA2CNT_H: return trigger_dma(2, value);
case REG_DMA3CNT_H: return trigger_dma(3, value);
// Timer counter reload
case REG_TM0D: count_timer(0); break;
case REG_TM1D: count_timer(1); break;
case REG_TM2D: count_timer(2); break;
case REG_TM3D: count_timer(3); break;
/* Timer control register (0..3)*/
case REG_TM0CNT: trigger_timer(0, value); break;
case REG_TM1CNT: trigger_timer(1, value); break;
case REG_TM2CNT: trigger_timer(2, value); break;
case REG_TM3CNT: trigger_timer(3, value); break;
// Serial port registers
case REG_SIOCNT:
return write_siocnt(value);
case REG_RCNT:
return write_rcnt(value);
// Interrupt flag, clears the bits it tries to write
case REG_IF:
write_ioreg(REG_IF, read_ioreg(REG_IF) & (~value));
break;
// Register writes with side-effects, can raise an IRQ
case REG_IE:
case REG_IME:
write_ioreg(ioreg, value);
return check_interrupt();
// Read-only registers
case REG_P1:
case REG_VCOUNT:
break; // Do nothing
case REG_WAITCNT:
write_ioreg(REG_WAITCNT, value);
reload_timing_info();
break;
// Registers without side effects
default:
write_ioreg(ioreg, value);
break;
}
return CPU_ALERT_NONE;
}
cpu_alert_type function_cc write_io_register8(u32 address, u32 value)
{
if (address == 0x301) {
if (value & 1)
reg[CPU_HALT_STATE] = CPU_STOP;
else
reg[CPU_HALT_STATE] = CPU_HALT;
return CPU_ALERT_HALT;
}
// Partial 16 bit write, treat like a regular merge-write
if (address & 1)
value = (value << 8) | (read_ioreg(address >> 1) & 0x00ff);
else
value = (value & 0xff) | (read_ioreg(address >> 1) & 0xff00);
return write_io_register16(address & 0x3FE, value);
}
cpu_alert_type function_cc write_io_register32(u32 address, u32 value)
{
// Handle sound FIFO data write
if (address == 0xA0) {
sound_timer_queue32(0, value);
return CPU_ALERT_NONE;
}
else if (address == 0xA4) {
sound_timer_queue32(1, value);
return CPU_ALERT_NONE;