[core] code format

lnis-uofu · Nov 14, 2024 · d121538 · d121538
1 parent 07cbfa6
commit d121538
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Showing 3 changed files with 7 additions and 4 deletions.
diff --git a/openfpga/src/fpga_spice/spice_grid.cpp b/openfpga/src/fpga_spice/spice_grid.cpp
@@ -290,7 +290,8 @@ static void print_spice_physical_tile_netlist(
   if (true == is_io_type(phy_block_type)) {
     SideManager side_manager(border_side);
     VTR_LOG("Writing SPICE Netlist '%s' for physical tile '%s' at %s side ...",
-            spice_fname.c_str(), phy_block_type->name.c_str(), side_manager.c_str());
+            spice_fname.c_str(), phy_block_type->name.c_str(),
+            side_manager.c_str());
   } else {
     VTR_LOG("Writing SPICE Netlist '%s' for physical_tile '%s'...",
             spice_fname.c_str(), phy_block_type->name.c_str());

diff --git a/openfpga/src/fpga_verilog/verilog_grid.cpp b/openfpga/src/fpga_verilog/verilog_grid.cpp
@@ -315,7 +315,8 @@ static void print_verilog_physical_tile_netlist(
     SideManager side_manager(border_side);
     VTR_LOG(
       "Writing Verilog Netlist '%s' for physical tile '%s' at %s side ...",
-      verilog_fpath.c_str(), phy_block_type->name.c_str(), side_manager.c_str());
+      verilog_fpath.c_str(), phy_block_type->name.c_str(),
+      side_manager.c_str());
   } else {
     VTR_LOG("Writing Verilog Netlist '%s' for physical_tile '%s'...",
             verilog_fpath.c_str(), phy_block_type->name.c_str());

diff --git a/openfpga/src/tile_direct/build_tile_direct.cpp b/openfpga/src/tile_direct/build_tile_direct.cpp
@@ -355,8 +355,9 @@ static void report_direct_from_port_and_to_port_mismatch(
     "From_port '%s[%lu:%lu] of direct '%s' does not match to_port "
     "'%s[%lu:%lu]'!\n",
     from_tile_port.get_name().c_str(), from_tile_port.get_lsb(),
-    from_tile_port.get_msb(), vpr_direct.name.c_str(), to_tile_port.get_name().c_str(),
-    to_tile_port.get_lsb(), to_tile_port.get_msb());
+    from_tile_port.get_msb(), vpr_direct.name.c_str(),
+    to_tile_port.get_name().c_str(), to_tile_port.get_lsb(),
+    to_tile_port.get_msb());
 }
 
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