some questions about timing report

[Chris202305]

vpr_arch：k4_N4_tileable_40nm.xml openfpga_arch：k4_N4_40nm_cc_openfpga_40nm.xml

grid_io_top_2_6.gpio[14] --> grid_io_top_2_6.io_inpad( gpio 42.43ps) --> grid_io_top_2_6.bottom_pin_inpad[6] --> sb_2_5 MUX(inv 10ps + tap_buf 10ps + Tgate 40ps) --> cbx_2_5 --> sb_1_5 (inv 10ps + tap_buf 10ps + Tgate 20ps)--> cby_1_5 --> sb_1_4 --> cby_1_4 --> sb_1_3 MUX(inv 10ps + tap_buf 10ps + Tgate 40ps)--> cbx_2_3 --> sb_2_3 --> cbx_3_3 --> sb_3_3 --> cbx_4_3 --> sb_4_3 --> cbx_5_3 MUX(inv 10ps + tap_buf 10ps + Tgate 30ps)--> clb_5_3

When tracing the timing paths starting from the initial point and calculating based on the delay information provided in the architecture document, I observed a discrepancy between the actual delay (66+62+68+72=269ps) and the theoretically calculated delay (60+40+60+50=210ps). Could you please clarify which factors contribute to this additional delay? Is it related to wire delay, and if so, how is the wire delay calculated? If not, could you kindly point out any delay factors that I might have overlooked in my calculations?