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Make spacing in Verilator top same as rest
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marnovandermaas committed Apr 5, 2024
1 parent f5fcf88 commit 7ab9775
Showing 1 changed file with 14 additions and 14 deletions.
28 changes: 14 additions & 14 deletions dv/verilator/top_verilator.sv
Original file line number Diff line number Diff line change
Expand Up @@ -13,35 +13,35 @@ module top_verilator (input logic clk_i, rst_ni);
// Instantiating the Sonata System.
sonata_system u_sonata_system (
// Clock and Reset
.clk_sys_i (clk_i),
.clk_sys_i (clk_i ),
.rst_sys_ni(rst_ni),

// UART TX and RX
.uart_rx_i (uart_sys_rx),
.uart_tx_o (uart_sys_tx),

// Remaining IO
.gp_i (0),
.gp_o ( ),
.pwm_o ( ),
.spi_rx_i (0),
.spi_tx_o ( ),
.spi_sck_o ( ),
.gp_i (0),
.gp_o ( ),
.pwm_o ( ),
.spi_rx_i (0),
.spi_tx_o ( ),
.spi_sck_o( ),

// CHERI output
.cheri_err_o ( ),
.cheri_en_o ( )
.cheri_err_o(),
.cheri_en_o ()
);

// Virtual UART
uartdpi #(
.BAUD(BaudRate),
.FREQ(ClockFrequency)
.BAUD ( BaudRate ),
.FREQ ( ClockFrequency )
) u_uartdpi (
.clk_i,
.rst_ni,
.active (1'b1 ),
.tx_o (uart_sys_rx),
.rx_i (uart_sys_tx)
.active(1'b1 ),
.tx_o (uart_sys_rx),
.rx_i (uart_sys_tx)
);
endmodule

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